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Datasheet: GP2015FP1Q (Zarlink Semiconductor Inc.)

Miniature GPS Receiver RF Front End ; Package Type = LQFP ; No. Of Pins = 48

 

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Zarlink Semiconductor Inc.
GP2015
GPS Receiver RF Front End
DS4374
ISSUE 3.1
February 2002
Ordering Information
GP2015 IG FP1N (Trays, Bake & Drypack)
(Supersedes GP2015 IG FP1R)
GP2015 IG FP1Q (Tape mounted, Bake & Drypack)
48 pin TQFP (-40
C to +85
C)
The GP2015 is a small format RF Front-end for Global
Positioning System (GPS) receivers. Equivalent in
performance to the GP2010 but in a TQFP package, this
product is suited for size-critical applications as the RF area
can be reduced by a factor of two to three using miniature
surface mount passive components The GP2015 is designed
to operate from either 3 or 5 Volt supplies.
The input to the device is the L1 (1575.42MHz) Coarse-
Acquisition (C/A) code Global Positioning signal from an
antenna (via a low-noise pre-amplifier). The output is 2-bit
quantised for subsequent signal processing in the digital
domain. The GP2015 contains an on-chip synthesiser, mixers,
AGC and a quantiser which provides Sign and Magnitude
digital outputs. A minimum of external components is required
to make a complete GPS front-end.
The device has been designed to operate with the GP2021
12-channel GPS Correlator and GP4020 GPS Baseband
Processor, both available from Zarlink Semiconductor.
Features
Ultra miniature TQFP package
Low Voltage Operation (3V - 5V)
Low Power - 200mW typ. (3V supply)
C/A Code Compatible
On-chip PLL Including Complete VCO
Triple Conversion Receiver
48-Lead Surface Mount Quad Flat-Pack Package
Sign and Magnitude Digital Outputs
Compatible with GP2021 and GP4020 Correlators
Applications
C/A Code Global Positioning by Satellite Receivers
Time Standards
Navigation
Surveying
Related Products and Publications
Data
Reference
Twelve-Channel Correlator
GPS Baseband Processor
GPS ORION 12 Channel GPS
Receiver Reference Design
GP2000 GPS Receiver
Hardware Design
GP2010/GP2015: Using Murata
SAFJA35M4WC0Z00 SAW Filter
GP2021
GP4020
App. Note
App Note.
App. Brief
DS4057
DS5134
AN4808
AN4855
AB5202
Part
Description
1
2
3
4 5 6
7 8
9 10 11 12
36 35 34 33 32 31 30 29 28 27 26 25
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
GP2015
FP48
Figure 1 - Pin connections - top view
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
IF Output
PLL Filter 1
PLL Filter 2
V
EE
(OSC)
V
CC
(OSC)
V
EE
(OSC)
V
EE
(REG)
PRef
PReset
V
EE
(IO)
CLK
N/C
N/C
MAG
SIGN
OPCIK-
OPCIK+
V
DD
(IO)
PD
N
TEST
LD
V
EE
(DIG)
AGC -
AGC +
Name
N/C
V
CC
(DIG)
REF 2
REF 1
V
CC
(RF)
V
EE
(RF)
V
EE
(RF)
RF Input
V
EE
(RF)
V
EE
(RF)
V
CC
(RF)
N/C
O/P 1-
O/P 1+
V
CC
(2)
I/P 2-
I/P 2+
V
EE
(IF)
V
EE
(IF)
O/P 2-
O/P 2+
V
CC
(3)
I/P 3-
I/P 3+
Pin
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
2
GP2015
IF STRIP
The input signal to the GP2015 is the GPS L1 signal
received via an antenna and a suitable LNA. The L1 input is
a spread spectrum signal at 1575.42MHz with 1.023Mbps
BPSK modulation. The signal level at the antenna is about
-130dBm, spread over a 2.046MHz bandwidth, so the wanted
signal is actually buried in noise. The high RF input
compression point of the GP2015 means that with subsequent
IF filtering it is possible to reject large out of band jamming
signals, in particular 900MHz as used by mobile
telephones.The on-chip PLL generates the first local-oscillator
frequency at 1400MHz. The output of the front-end mixer
(Stage 1) at 175.42 MHz can then be filtered before being
applied to the second stage. The double-balanced stage 1
mixer outputs are open-collectors, and require external dc
bias to V
CC
.
The second stage contains further gain and a mixer
with a local oscillator signal at 140 MHz giving a second IF at
35.42 MHz. The second stage mixer is also double-balanced
with open-collector outputs requiring external dc bias to V
CC
.
The signal from stage 2 is passed through an external
filter with a 1dB bandwidth of 1.9MHz. The performance of
this filter is critical to system performance and it is
recommended that a SAW filter is used (part number
SAFJA35M4WC0Z00 , available from Murata). The output of
the filter then feeds the main IF amplifier. This includes 2
AGC amplifiers and a third mixer with a local oscillator signal
at 31.111 MHz giving a final IF at 4.309 MHz. There is an on-
chip filter after the third mixer which provides filtering centred
on 4.309 MHz. The IF output, which has 1k
output
impedance, is provided for test purposes. All of the signals
within the IF amplifier are differential including the filter inputs
ABSOLUTE MAXIMUM RATINGS
(Non-simultaneous)
Max. Supply Voltage
7V
Max. RF Input
+15dBm
Max. voltage on any pin
V
CC
/V
DD
+ 0.5V
except LD (pin 21) and PReset (pin 9), which are 5.5V Min.
voltage on any pin
V
EE
- 0.5V
Storage Temperature
-65
C to +150
C
Operation Junction Temperature
-40
C to +150
C
10MHz Reference Input
1.5V pk -pk
ESD PROTECTION
The GP2015 device is static sensitive. The most
sensitive pins withstand a 750V test by the human body
model. Therefore, ESD handling precautions are essential to
avoid degradation of performance or permanent damage to
this device.
PRODUCT DESCRIPTION
The GP2015 receives the 1575.42MHz signal
transmitted by GPS satellites and converts it to a 4.309MHz
IF, using triple down-conversion. The 4.309MHz IF is sampled
to produce a 2-bit digital output. If the GP2015 is used in
conjunction with the GP2021 correlator, then the GP2021
provides a sampling clock of 5.714MHz. This converts the IF
to a 1.405MHz 2-bit digital output at TTL levels.
The GP2015 can operate from a single supply from
+3V (nominal) to +5V (nominal).
A block diagram of the circuit is shown in figure 2.
FRONT
END
MIXER
VCO
PLL
LOOP
FILTER
EXTERNAL
LOOP
FILTER
2nd
STAGE
MIXER
175.42MHz FILTER
AGC
AGC
3rd
STAGE
MIXER
4.3MHz
FILTER
35.42MHz FILTER
5
5
5
31.11MHz
140MHz
PHASE
DETECTOR
VOLTAGE
REGULATOR
1.400GHz
PHASE-
LOCKED
LOOP
PLL REF I/P
10MHz (REF 2)
40MHz CLOCK O/P
(FOR CORRELATOR
CHIP)
(OPCIK +/-)
PLL LOCK
LOGIC O/P
(LD)
1. 400GHz
(TEST)
AGC
CONTROL
+Vr
-Vr
SIGN
O/P
LATCH
MAG
O/P
LATCH
SIGN
TTL O/P
MAG
TTL O/P
SAMPLE
CLOCK I/P (CLK)
(5.71MHz TTL)
IF Output
(4.309MHz)
A -> D
CONVERTER
RF Input
L1
(1575.42MHz)
PLL
REFERENCE
OSCILLATOR
AGC CAPACITOR
REF 1 I/P
(FOR USE WITH
CRYSTAL REF
ONLY)
+1.21V
POWER-ON
REFERENCE
I/P
(PREF)
POWER-ON
RESET O/P
(PRESET)
POWER
CONTROL
POWER
DOWN I/P
(PDn)
POWER-ON
RESET
(1)
(15)
(14)
(11)
(9)
(19)
(8)
(20)
(28)
(16,17)
(27)
(21)
(3)
(2)
(32)
(37,38)
(40,41)
(44,45)
(47,48)
(23)
(24)
_
+
2
7
4
9
Figure 2 - Block diagram of GP2015
3
GP2015
and outputs, except the IF output (pin 1), to reduce any
common mode interference.
The IF output is fed to a 2-bit quantiser which provides
sign and magnitude (MSB and LSB) outputs. The magnitude
data controls the AGC loop, such that on average the
magnitude bit is set (high) 30% of the time. The AGC time
constant is set by an external capacitor.
The sign and magnitude data, SIGN (pin 15) and MAG (pin
14), are latched by the rising edge of the sample clock, CLK
(pin 11), which is normally derived from the correlator; the
GP2021 provides a 5.714MHz (=40/7) clock, giving a sampled
IF centred on 1.405MHz.
The Digital Interface circuits use a separate power-supply,
V
DD
(IO), which would normally be shared with the correlator
to minimise crosstalk between the analog and digital sections
of the device.
ON-CHIP PHASE-LOCKED LOOP SYNTHESISER
All of the local oscillator signals are derived from an on
chip phase locked loop synthesiser. This includes a 1400MHz
VCO complete with on-chip tank circuit, dividers and phase
detector, with external loop filter components. A 10.000MHz
reference frequency is required for the PLL. This can be
achieved by attaching an external 10.000MHz crystal to the
on-chip PLL reference oscillator (see figure 5). However in
most applications the user will need an external source, such
as a TCXO, to provide greater frequency stability (see figure
6). An external reference should be ac coupled to REF2 (pin
27); REF 1 (pin 28) should be left open circuit.
The three local oscillator signals 1400MHz, 140.0MHz
and 31.11MHz are derived from the 1400MHz synthesiser
output. The synthesiser also provides a 40 MHz balanced
differential output clock (pins 16 & 17) which can be used to
clock the GP2021 correlator. The clock is a low level differential
signal which helps minimise interference with the analog
areas of the circuit. A PLL lock-detect output, LD (pin 21), is
also provided, which is logic high when the PLL is phase-
locked to the 10.000MHz reference signal.
The VCO power-supply incorporates an on-chip
regulator to improve the noise-immunity of the PLL. This
feature is only available when operating with a 5 volt (nominal)
supply which is regulated to 3.3 volts internally. This internal
regulated supply is referenced to V
CC
(OSC) (pin 5). Figure 7
shows the required connections for both 3 volt and 5 volt
operation.
A further feature of the circuit is the TEST input (pin
20). When this input is held high the PLL is unlocked with the
VCO at its maximum frequency.
POWER-DOWN CAPABILITY
A power down function is provided on the GP2015, to
limit power consumption. This powers down the majority of
the circuit except the "power-on reset" function (see below).
If the power down feature is not required, the Power-
down input, PD
n
(pin 19), should be connected to 0V dc
(=Vee/Ground).
POWER-ON RESET FUNCTION
The GP2015 includes a voltage detector which
operates from the digital interface supply. This circuit is used
to produce a TTL logic low output while the GPS receiver
power supply is switching on, and produces a logic high
output when the power supply voltage has achieved a
nominal value. This output can be used to disable the
GP2021 correlator while the power supply is switching on. An
internal bandgap reference of approximately +1.21V is
compared with the voltage on a sense pin, PRef (pin 8); when
the voltage on this pin exceeds the reference, a TTL logic
high level appears at the Power-on Reset output, PReset (pin
9). Thus, if the sense input voltage is derived from an external
resistive divider from the Digital Interface supply, V
DD
(IO)
(pin 16), such that the sense voltage at nominal V
CC
is V
S
,
then the supply threshold, Vcc(thresh), at which the PReset
output goes to logic high is:-
For a V
CC
(nom) of 5.0V, V
CC
(thresh) may be set to approx.
4.0V, giving V
S
of 1.5V.
For a V
CC
(nom) of 3.0V, V
CC
(thresh) may be set to approx.
2.4V, giving V
S
of 1.5V.
ADDITIONAL INFORMATION
All the digital inputs and outputs can use a separate
power supply to help prevent digital switching transitions
interacting with the analog sections of the device, and as an
additional precaution, the digital inputs and outputs are on
the opposite side of the device to the critical analog pins.
V
S
= V
CC
(nom) x 1.21
V
CC
(thresh)
4
GP2015
ELECTRICAL CHARACTERISTICS
The Electrical Characteristics are guaranteed over the following range of operating conditions (see Fig. 3 for test circuit):
Industrial (I) grade:
T
AMB
= -40
C to +85
C
Supply voltage:
V
CC
and V
DD
= +2.7V to +5.5V
Test conditions (unless otherwise stated):
Supply voltages:
V
CC
= +2.7V and +5.5V, V
DD
= +2.7V and +5.5V
Test temperature:
Industrial (I) grade product: +25
C
mA
mA
mA
mA
mV
s
dB
dB
dBm
nH
dB
dB
mV rms
dB
dB
dB
k
mV rms
k
dB
dB
dB
%
%
ms
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
Pins 5, 26, 29, 35, 39, 46
Pin 18
Pins 5, 26, 29, 35, 39, 46
Pin 18
Between any V
CC
/V
DD
pins (Note 7)
(Note 7)
R
O
= 600
(Note 2)
F
IN
= 1575.42MHz
Z
S
= 50
(Note 7)
Pin 32 (Notes 1 and 7)
(Notes 1 and 7)
Pins 37 & 38 (Note 8)
F
IN
= 1224.58MHz (Note 7)
F
IN
= 175.42MHz
Pins 40 & 41 (Note 8)
Pins 44 & 45 (Note 8)
(Note 6)
F
IN
= 35.42MHz
(Note 3)
Pins 47 & 48 (Note 8)
CW input (Note 3)
Pin 1(Note 8)
(Note 7 and 9)
C
AGC
= 100nF
15kHz Loop Bandwidth
(Note 7)
77
14.5
6
5
100
25
33
120
+1.0
60
40
SUPPLY CURRENT
Normal mode - Analog interface
- Digital interface
Power down mode - Analog interface
- Digital interface
Power Supply Differential
Power down Response time
IF STRIP
Front End/Mixer 1
Conversion Gain (G1)
Noise Figure
Input Compression (1dB)
Input Impedance
Differential Output Impedance
RF Input Image Rejection
Stage 2/Mixer 2
Conversion Gain (G2)
Input Compression (1dB)
Differential Input Impedance
Differential Output Impedance
Stage 3
High Gain (In terms of total strip)
High Gain (G3)
Gain Control Range
Differential Input Impedance
IF Output amplitude
IF Output impedance
4.3MHz Filter Response
Flatness 4.3
1MHz
Rejection @ 0.5MHz
@ 50MHz
2 BIT QUANTISER
Sign Duty Cycle
Mag Duty Cycle
AGC Time Constant
ON-CHIP PLL SYNTHESISER
Phase Noise
1kHz
10kHz
100kHz
1MHz
5MHZ
50MHz
PLL Spurs
Characteristic
Value
Typ.
Max.
55
9
3
3
3
18
9
-16
17
3.4
700
7
27
14
700
500
75
60
1
85
1
14
70
50
30
2
-68
-75
-88
-110
-120
-120
-50
Conditions
Units
11
-22
22
5
106-G1-G2
60
-1.5
45
40
20
Min.
(Note 10)
(Note 7)
5
GP2015
Notes on Electrical Characteristics:- All RF measurements are made with appropriate matching to the input or output
impedances, such as balun transformers, and levels refer to matched 50ohm ports (see figure 3 for test circuit)
1.
RF input impedance (series) without input matching components connected - expressed as Real impedance with reactive
inductor value. Measured at 1575.42MHz.
2.
Input matched to 50ohm, output loaded wlth 600ohm differential
3.
Maximum Stage 3 input signal amplitude for correct AGC operation = 20mV rms.
4.
VCO regulator voltage measured with respect to Vcc (OSC) - pin 5.
5.
The OPCLK outputs are differential and are referenced to V
DD
.
6.
Minimum gain requirement expressions
MHz
MHz
V
MHz/V
V/rad
V pk-pk
k
ms
dB
V
V
A
A
V
V
ns
V
V
mV p-p
%
V
V
V
A
(Note 4)
(Note 7)
Pin 27
(Note 11)
From Power up (Note 7)
(Note 7)
Pins 11, 19, 20
V
IH
= V
DD
V
IL
= V
EE
Pins 15, 14
I
O
= -0.5mA
I
O
= 0.5mA
CL = 15pF, RL = 15k
(Note 7)
Pins 16 & 17
(Note 5)
CL = 15pF (GND) (Note 7)
CL = 5pF (Diff) (Note 7)
(Note 7)
Pins 21 and 9
I
O
= 0.5mA
I
O
= -10
A
Pin 8
1386
3.5
240
1.2
V
DD
0.5
10
0.5
V
DD
-0.8
0.5
1.35
10
Characteristic
Value
Typ.
Max.
Min.
3.3
150
5.3
0.6
5
6
150
20
V
DD
-1
V
OH
-0.1
220
43
0.2
V
DD
Conditions
Units
1414
3
50
0.1
2
0
-300
V
DD
-1
V
DD
-1.25
V
DD
-1
1.1
-10
VCO Maximum Lock Frequency
VCO Minimum Lock Frequency
VCO regulator output voltage
VCO Gain
Phase Detector Gain
10MHz Reference Input
10MHz Reference Input Impedance
PLL Lockup Time
PLL Loop Gain
DIGITAL INTERFACES
Sample Clock, Power Down,
Test Inputs.
V
IH
V
IL
Input Current High I
IH
Input Current Low I
IL
Sign/Mag Outputs
V
OH
V
OL
Sample Clock to Sign/Mag Delay
40MHz Clock Output
High Level (V
OH
)
Low Level (V
OL
)
Output (differential)
Duty Cycle
LD (PLL Lock)/PReset Outputs
Low Level (V
OL
)
High Level (V
OH
)
Power-on Reset comparator input
Power Reset Reference Level
Power Reset Reference Input Current
-7dBm
<
-174dBm/Hz + 19dB + G1 + G2 + G3 - 21dB + 63dB
where:
-7dBm
=
typical IF Output level with AGC active (equivalent to 100mV rms)
-174dBm/Hz
=
background noise level at RF input
19dB
=
sum of LNA gain and noise figure
-21dB
=
total loss in 175MHz and 35MHz filters
63dB
=
summation of noise over a 2MHz bandwidth
Rearranging the above expression gives G1 + G2 + G3 > 106dB.
7.
This parameter is not production tested.
8.
This impedance is toleranced at +/-30% and is not production tested.
9.
Roll off occurs in on-chip capacitive coupling IF Output to input of ADC circuit. Not measurable at IF Output.
10. CW input on pins 47 & 48 of 35.42MHz at 7mV rms.
11. This input impedance applies to the typical input level. The impedance is level dependent and is not tested or guaranteed.
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