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Datasheet: ARM610 (Zarlink Semiconductor Inc.)

General purpose 32-bit microprocessor

 

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Zarlink Semiconductor Inc.
ARM610
Data Sheet
Zarlink Part Number: P610ARM-B/KG/FPNR
Notes
1) The original P610ARM/KG/FPNR is obsolete
2) This datasheet includes the performance data previously supplied in supplement
MS4397 - Jan 1996
DS3554
ISSUE 3.2
October 2001
Manufactured under licence from Advanced RISC Machines Ltd
ARM and the ARM logo are trademarks of Advanced RISC Machines Ltd
Advanced RISC Machines Ltd 1999
P610ARM-B/KW/FPNR
ARM610 Data Sheet
Preface-ii
Preface
The ARM610 is a general purpose 32-bit microprocessor with
4
kByte cache, write buffer and Memory
Management Unit (MMU) combined in a single chip. The ARM610 offers high level RISC performance yet
its fully static design ensures minimal power consumption, making it ideal for portable, low-cost systems.
The innovative MMU supports a conventional two-level page-table structure and a number of extensions
which make it ideal for embedded control, UNIX and Object Oriented systems. This results in a high
instruction throughput and impressive real-time interrupt response from a small and cost-effective chip.
Applications
The ARM610 is ideally suited to those applications requiring RISC performance from a compact, power
efficient processor. These include:
Personal computer devices eg.PDAs
High-performance real-time control systems
Portable telecommunications
Data communications equipment
Consumer products
Automotive
Feature Summary
High performance RISC
25 MIPS sustained @ 33 MHz
(33 MIPS peak)
Fast sub microsecond interrupt response
for real-time applications
Memory Management Unit (MMU)
support for virtual memory systems
Excellent high-level language support
4kByte of instruction & data cache
Big and Little Endian operating modes
Write Buffer
enhancing performance
IEEE 1149.1 Boundary Scan
Fully static operation, low power consumption
ideal for power sensitive applications
144 Thin Quad Flat Pack (TQFP) package
Address
Bus
JTAG
ARM6
Write
MMU
4Kbyte
Control
CPU
Buffer
Cache
ARM610 Data Sheet
Contents-1
1
Introduction
1-1
1.1
Introduction
1-2
1.2
Block Diagram
1-4
1.3
Functional Diagram
1-5
2
Signal Description
2-1
2.1
Signal Description
2-2
3
Programmer's Model
3-1
3.1
Introduction
3-2
3.2
Register Configuration
3-2
3.3
Operating Mode Selection
3-3
3.4
Registers
3-3
3.5
Exceptions
3-6
3.6
Reset
3-10
4
Instruction Set
4-1
4.1
Instruction Set Summary
4-2
4.2
The Condition Field
4-5
4.3
Branch and Branch with Link (B, BL)
4-7
4.4
Data Processing
4-9
4.5
PSR Transfer (MRS, MSR)
4-17
4.6
Multiply and Multiply-Accumulate (MUL, MLA)
4-22
4.7
Single Data Transfer (LDR, STR)
4-24
4.8
Halfword and Signed Data Transfer
4-30
4.9
Block Data Transfer (LDM, STM)
4-36
4.10
Single Data Swap (SWP)
4-43
4.11
Software Interrupt (SWI)
4-45
4.12
Coprocessor Data Operations (CDP)
4-47
Contents
TOC
Contents
ARM610 Data Sheet
Contents-2
4.13
Coprocessor Data Transfers (LDC, STC)
4-49
4.14
Coprocessor Register Transfers (MRC, MCR)
4-53
4.15
Undefined Instruction
4-55
4.16
Instruction Set Examples
4-56
5
Configuration
5-1
5.1
Configuration
5-2
5.2
Internal Coprocessor Instructions
5-2
5.3
Registers
5-2
6
Instruction and Data Cache (IDC)
6-1
6.1
Introduction
6-2
6.2
Cacheable Bit - C
6-2
6.3
Updateable Bit - U
6-2
6.4
IDC Operation
6-2
6.5
IDC Validity
6-3
6.6
Read-Lock-Write
6-3
6.7
IDC Enable/Disable and Reset
6-4
7
Write Buffer (WB)
7-1
7.1
Introduction
7-2
7.2
Bufferable Bit
7-2
7.3
Write Buffer Operation
7-2
8
Coprocessors
8-1
8.1
Overview
8-2
9
Memory Management Unit
9-1
9.1
Memory Management Unit (MMU)
9-2
9.2
MMU Program Accessible Registers
9-2
9.3
Address Translation
9-3
9.4
Translation Process
9-4
9.5
Level One Descriptor
9-5
9.6
Page Table Descriptor
9-5
9.7
Section Descriptor
9-6
9.8
Translating Section References
9-7
9.9
Level Two Descriptor
9-8
9.10
Translating Small Page References
9-9
9.11
Translating Large Page References
9-10
9.12
MMU Faults and CPU Aborts
9-11
9.13
Fault Address and Fault Status Registers (FAR and FSR)
9-11
9.14
Domain Access Control
9-13
9.15
Fault Checking Sequence
9-14
9.16
External Aborts
9-16
9.17
Interaction of the MMU, IDC and Write Buffer
9-17
9.18
Effect of Reset
9-18
10
Bus interface
10-1
10.1
Introduction
10-2
10.2
ARM610 Cycle Speed
10-2
Contents
ARM610 Data Sheet
Contents-3
10.3
Cycle Types
10-2
10.4
Memory Access
10-2
10.5
Read/Write
10-3
10.6
Byte/Word
10-3
10.7
Maximum Sequential Length
10-3
10.8
Memory Access Types
10-5
10.9
ARM610 Cycle Type Summary
10-9
11
Boundary-Scan Test Interface
11-1
11.1
Introduction
11-2
11.2
Overview
11-2
11.3
Reset
11-3
11.4
Pullup Resistors
11-3
11.5
Instruction Register
11-3
11.6
Public Instructions
11-3
11.7
Test Data Registers
11-7
11.8
Boundary-Scan Interface Signals
11-10
12
DC Parameters
12-1
12.1
Absolute Maximum Ratings
12-2
12.2
DC Operating Conditions
12-2
12.3
DC Characteristics
12-3
13
AC Parameters
13-1
13.1
Test Conditions
13-2
13.2
Relationship between FCLK and MCLK
13-2
13.3
Main Bus Signals
13-4
14
Physical details
14-1
14.1
Physical Details
14-2
15
Pinout
15-1
15.1
Pinout
15-2
Backward Compatibility
A-1
Backward Compatibility
A-2
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