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Datasheet: YMU759C-QZ (YAMAHA Corp.)

MA-2

 

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YAMAHA Corp.
YMU759
MA-2
YAMAHA CORPORATION
YMU759 CATALOG
CATALOG No.:LSI-4MU759A0
2000.5
PRELIMINARY
May 8 .2000
Outline
YMU759 is a synthesis LSI for portable telephone that is capable of playing high quality music by utilizing FM
synthesizer and ADPCM decoder that are included in this device. As a synthesis, YMU759 is equipped with
Yamaha's original FM synthesizer, with which the device is capable of simultaneously generating up to 16 voices
with different tones. Since the device is capable of generating ADPCM data simultaneously synchronous with the
play of the FM synthesizer, various sampled voices can be used as sound effects.
Since the play data of YMU759 are interpreted at anytime through FIFO, the length of the data (playing period) is
not limited, so the device can flexibly support applications such as incoming call melody distribution service.
The hardware sequencer built in this device allows playing of complex music without giving excessive load to the
CPU of the portable telephones. Moreover, the registers of the FM synthesizer can be operated directly for real time
sound generation, allowing, for example, utilization of various sound effects when using the game software installed
in the portable telephone.
Features
Equipped with
FM sound generator function and ADPCM playback function.
Number of voices simultaneously generated
When only 2-operator tones are used: up to 16 voices can be generated simultaneously.
When only 4-operator tones are used: up to 8 voices can be generated simultaneously.
Built-in 4-bits 1ch ADPCM decoder, and supports two kinds of sampling frequency, 4 kHz and 8 kHz.
Built-in output 550mW(AVDD=3.6V) speaker amplifier:
Built-in hardware sequencer.
Built-in circuit for sound quality correcting equalizer.
Supports stereophonic output.
Built-in 16-bit stereophonic D/A converter.
Provided with a stereophonic analog output terminal for headphone.
4 wire serial interface or 12 wire parallel interface can be selected.
PLL is built-in to support master clock input in 2 MHz to 20 MHz range.
Supports power down mode. (Typical current: 1 uA or less)
Power supply is divided into analog power supply for speaker amplifier and power supply for the others.
Analog power supply for speaker amplifier (SPVDD): 2.7V~4.5V(Typ 3.6V).
Digital power supply for the others(VDD): 2.7V~3.3V(Typ 3.0V)
32-pin plastic QFN.
The contents of this booklet are target specifications and they are subject to change without
a prior notice. Please check the finalized specifications before actually using this LSI.
YMU759
-2-
Terminal configuration
<32pin QFN Top View>
16
15
14
13
12
11
10
SPVSS
SPVDD
EQ3
EQ2
EQ1
HPOUT-R
HPOUT-L/MONO
1 2 3 4 5 6 7 8 9
VR
EF
VSS
VDD
P
LLC
I
FSE
L
/RST
/I
RQ
EXT
1
CLK
I
25 24 23 22 21 20 19 18 17
S
P
O
U
T
1
S
P
O
U
T
2
E
X
T
2
D
7
D
6
D
5
D
4
D
3
D
2
26
27
28
29
30
31
32
D1
D0
/WR
SDIN (/CS)
SYNC (A0)
SCLK (/RD)
SDOUT
YMU759
-3-
Terminal functions
No. Name
I/O
Function
1 CLKI
Ish
Clock input (2
~
20MHz)
2
EXT1
O
External device control terminal 1
3 /IRQ
O
Interruption output
4 /RST
Ish
Hardware reset input
5 IFSEL
I
CPU I/F selection L: Serial I/F, H: Parallel I/F
6 PLLC
A
Connection of capacitor for built in PLL
Connect 0.01
F (expected) capacitor between this terminal and VSS.
7 VDD
-
Digital power supply (Typically +3.0V)
Connect 0.1
F and 4.7
F capacitors between this terminal and VSS
8 VSS
-
Ground
9 VREF
A
Analog reference voltage.
Connect 0.1
F capacitor between this terminal and VSS
10
HPOUT-L / MONO
A
Headphone L channel output: can be switched to mono through register setting
11 HPOUT-R
A
Headphone R channel output
12 EQ1 A
Equalizer terminal 1
13 EQ2 A
Equalizer terminal 2
14 EQ3 A
Equalizer terminal 3
15
SPVDD
-
Analog power supply (Typically +3.6 V)
Connect 0.1
F and 4.7
F capacitors between this terminal and SPVSS
16 SPVSS -
Analog ground for speaker amplifier
17 SPOUT1 A
Speaker terminal 1
18 SPOUT2 A
Speaker terminal 2
19
EXT2
O
External device control terminal 2
20
D7
I/O
Parallel I/F data bus 7
21
D6
I/O
Parallel I/F data bus 6
22
D5
I/O
Parallel I/F data bus 5
23 D4
I/O
Parallel I/F data bus 4 (To be open when IFSEL=L)
24 D3
I/O
Parallel I/F data bus 3 (To be open when IFSEL=L)
25 D2
I/O
Parallel I/F data bus 2 (To be open when IFSEL=L)
26 D1
I/O
Parallel I/F data bus 1 (To be open when IFSEL=L)
27 D0
I/O
Parallel I/F data bus 0 (To be open when IFSEL=L)
28 /WR
Ish
Parallel I/F write pulse (To be open when IFSEL=L)
29 SDIN
(/CS)
Ish
IFSEL= L Serial I/F data input
IFSEL= H Parallel I/F chip select input
30 SYNC
(A0)
Ish
IFSEL= L Serial I/F data take-in signal
IFSEL= H Parallel I/F address signal
31 SCLK
(/RD)
Ish
IFSEL= L Serial I/F bit clock input
IFSEL= H Parallel I/F read pulse
32 SDOUT
OD
Serial I/F data output (Pull up resistance is necessary for the outside)
Comment: Ish= Schmitt input, OD= open drain terminal, A= Analog terminal
YMU759
-
4
-
Block diagram
S
P
VDD
SPV
SS
CL
K
I
VDD
V
SS
P
LLC
CPU I/F
SYNC
SDIN
Pow
e
r
Down
Co
n
t
r
o
l
SCLK
/RST
Register
FM
Synthesizer
16 sound
generated
simultaneously
(Fs=49.7kHz)
16-bit DAC
Timing Generator
SDOUT
ADPCM
wave
FIFO
ADPCM
Playback
(Fs= 4 or 8 kHz)
HP
Vol L
EQ1
EQ2
EQ3
EQ
Vol
VREF
+
VREF
Vol
&
LPF
Vol
VREF
S
e
qu
en
cer
PLL
SP
Vol
SPOUT1
SPOUT2
Vol
HP
Vol R
Lch
Rch
Lch
Rch
/CS
/IRQ
4
A0
/WR
/RD
D0 - D7
IFSEL
SEL
E
C
T
ADPCM
Seq
FIFO
S
e
qu
en
cer
FM
FIFO
4
EXT1
EXT2
LED control
TIMER
Mi
x
&
S
e
l
ect
Analog power
supply for
speaker
amplifier
H
P
OUT
-
L
/
M
ONO
H
P
OUT
-
R
Vibrator control
YMU759
-
5
-
Outline of blocks
Explanation about outline of built-in each blocks and flow of the signal are follows.















CPU interface
Receives commands send from external CPU, interprets the contents, and then writes them into registers by index
address. Controls reading of designated register data.
As interfaces for controlling YMU759, 4 wire serial and 12 wire parallel interfaces are provided, which can be
selected through IFSEL terminal.
Registers
Register groups that control the LSI except for sequence data.
FM tone register data, various volumes and other control data are store here.
FIFO
Sequence data to move hardware sequencer and ADPCM wave data are stored in FIFO.
This device is equipped with four FIFOs for FM and two FIFOs for ADPCM.
The FIFOs for FM stores sequence data and those for ADPCM stores sequence and waveform data. The size of
FIFOs for FM is 96 bytes, the one for ADPCM data is 384 bytes, and the one for sequence data is 32 bytes.
Hardware sequencer
FIFO is provided as a previous stage of the sequencer which reads sequence data from FIFO to control FM and
ADPCM sections.
The sequence data are compatible with SMAF(Synthetic music Mobile Application Format) proposed by yamaha.
FM synthesis
This is a synthesis that uses Yamaha's original FM system. It is able to generate up to 16 voices simultaneously.
This section plays in accordance with commands from the sequencer.
It can also play by directly controlling various registers without using the sequencer.
The sampling frequency is 49.7 kHz that complies with stereophonic sound.

ADPCM playback
This section decodes 4 bit ADPCM data to 16 bit data by using the sampling frequency of 4 kHz or 8 kHz.
It can playback one voice. It playback according to command from sequencer.
And it can playback to control various register directly without using sequencer.
CP
U I
n
t
e
r
f
ace
Register
FIFO
Hardware
Sequencer
Clock
Generate
FM
Sound
Generator
ADPCM
Playback
DAC
Headphone
Output
EQ
Amplifier
Speaker
Amplifier
External
Parts
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