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Datasheet: EDI416S4030A-SI (White Electronic Designs Corporation)

Organization = 1Mx16x4 ; Speed MHZ = 83-100 ; Volt = 3.3 ; Package = 54 Tsop ii ; Temp = C,i ;

 

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White Electronic Designs Corporation
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
EDI416S4030A
January 2003 Rev.2
ECO # 14194
1M x 16 Bits x 4 Banks Synchronous DRAM
FEATURES
n
Single 3.3V power supply
n
Fully Synchronous to positive Clock Edge
n
Clock Frequency = 100, 83MHz
n
SDRAM CAS Latentency = 3 (100MHz), 2 (83MHz)
n
Burst Operation
Sequential or Interleave
Burst length = programmable 1,2,4,8 or full page
Burst Read and Write
Multiple Burst Read and Single Write
n
DATA Mask Control per byte
n
Auto Refresh (CBR) and Self Refresh
4096 refresh cycles across 64ms
n
Automatic and Controlled Precharge Commands
n
Suspend Mode and Power Down Mode
n
Industrial Temperature Range
P
IN
C
ONFIGURATION
DESCRIPTION
The EDI416S4030A is 67,108,864 bits of synchronous high
data rate DRAM organized as 4 x 1,048,576 words x 16
bits. Synchronous design allows precise cycle control with
the use of system clock, I/O transactions are possible on
every clock cycle. Range of operating frequencies, program-
mable burst lengths and programmable latencies allow the
same device to be useful for a variety of high bandwidth,
high performance memory system applications.
Available in a 54 pin TSOP type II package the EDI416S4030A
is tested over the industrial temp range (-40C to +85C)
providing a solution for rugged main memory applications.
FIG. 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
V
SS
NC/RFU
UDQM
CLK
CKE
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
V
DD
LDQM
WE
CAS
RAS
CE
BA
0
BA
1
A
10
/AP
A
0
A
1
A
2
A
3
V
DD
TERMINAL
CONNECTIONS
(T
OP
VEIW)
P
IN
D
ESCRIPTION
A
0-11
Address Inputs
BA
0
, BA
1
Bank Select Addresses
CE
Chip Select
WE
Write Enable
CLK
Clock Input
CKE
Clock Enable
DQ
0-15
Data Input/Output
L(U)DQM
Data Input/Output Mask
RAS
Row Address Strobe
CAS
Column Address Strobe
V
DD
Power (3.3V)
V
DDQ
Data Output Power
V
SS
Ground
V
SSQ
Data Output Ground
NC
No Connection
2
White Electronic Designs Corporation Westborough, MA (508) 366-5151
White Electronic Designs
EDI416S4030A
I
NPUT
/O
UTPUT
F
UNCTIONAL
D
ESCRIPTION
Symbol
Type
Signal
Polarity
Function
CLK
Input
Pulse
Positive Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
CKE
Input
Level
Active High
Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the clock,
CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
CE
Input
Pulse
Active Low
CE disable or enable device operation by masking or enabling all inputs except CLK, CKE and DQM.
RAS, CAS
Input
Pulse
Active Low
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be
WE
executed by the SDRAM.
BA
0
,BA
1
Input
Level
--
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A
0-11
defines the row address (RA
0-11
) when sampled at the
rising clock edge.
During a Read or Write command cycle, A
0-7
defines the column address (CA
0-7
) when sampled at the
A
0-11
,
rising clock edge. In addition to the row address, A
10
/AP is used to invoke Autoprecharge operation at
A
10
/AP
Input
Level
--
the end of the Burst Read or Write cycle. If A
10
/AP is high, autoprecharge is selected and BA
0
, BA
1
defines the bank to be precharged . If A
10
/AP is low, autoprecharge is disabled.
During a Precharge command cycle, A
10
/AP is used in conjunction with BA
0
, BA
1
to control which
bank(s) to precharge. If A
10
/AP is high, all banks will be precharged regardless of the state of BA
0
,
BA
1
. If A
10
/AP is low, then BA
0
, BA
1
is used to define which bank to precharge.
DQ
0-15
Input/Output
Level
--
Data Input/Output are multiplexed on the same pins.
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In
L(U)DQM
Input
Pulse
Mask
Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output
Active High
enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to
be written if it is low but blocks the Write operation if DQM is high.
V
DD
, V
SS
Supply
Power and ground for the input buffers and the core logic.
V
DDQ
, V
SSQ
Supply
Isolated power and ground for the output buffers to improve noise immunity.
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
EDI416S4030A
Parameter
Symbol
Max
Unit
Input Capacitance (A
0-11
, BA
0-1
)
C
I
1
4
pF
Input Capacitance (CLK, CKE, RAS,
C
I
2
4
pF
CAS, WE, CE, DQM)
Input/Output Capacitance (DQ
0-15
)
C
OUT
5
pF
A
BSOLUTE
M
AXIMUM
R
ATINGS
Stresses greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
R
ECOMMENDED
DC O
PERATING
C
ONDITIONS
(V
OLTAGE
R
EFERENCED
TO
: V
SS
= 0V, T
A
= -40C
TO
+85C)
C
APACITANCE
(T
A
= 25C, f = 1MH
Z
, V
DD
= 3.0V
TO
3.6V)
Parameter
Symbol
Min
Max
Units
Power Supply Voltage
V
DD
-1.0
+4.6
V
Input Voltage
V
IN
-1.0
+4.6
V
Output Voltage
V
OUT
-1.0
+4.6
V
Operating Temperature
T
OPR
-40
+85
C
Storage Temperature
T
STG
-55
+125
C
Power Dissipation
P
D
1.0
W
Short Circuit Output Current
I
OS
50
mA
Parameter
Symbol Min Typ
Max Unit
Notes
Supply Voltage
V
DD
3.0
3.3
3.6
V
Input High Voltage
V
IH
2.0
3.0 V
DD
+0.3
V
Input Low Voltage
V
IL
-0.3
--
0.8
V
Output High Voltage
V
OH
2.4
--
--
V
(I
OH
= -2mA)
Output Low Voltage
V
OL
--
--
0.4
V
(I
OL
= 2mA)
Input Leakage Voltage
I
IL
-5
--
5
mA
Output Leakage Voltage
I
OL
-5
--
5
mA
O
PERATING
C
URRENT
C
HARACTERISTICS
(V
CC
= 3.6V, T
A
= -40C
TO
+85C)
Parameter
Symbol
Test Condition
-10
-12
Units Notes
Operating Current (One Bank Active)
I
CC
1
Burst Length = 1, t
RC
t
RC
(min)
140
125
mA
1
Operating Current (Burst Mode)
I
CC
4
Page Burst, 2 banks active, t
CCD
= 2 clocks
200
165
mA
1
Precharge Standby Current in Power Down Mode
I
CC
2
P
CKE
V
IL
(max), t
CC
= 15ns
2
2
mA
I
CC
2
PS
CKE, CLK
V
IL
(max), t
CC
=
, Inputs Stable
2
2
mA
I
CC
1
N
CKE = V
IH
, t
CC
= 15ns
50
50
mA
Precharge Standby Current in Non-Power Down Mode
Input Change every 30ns
I
CC
1
NS
CKE
V
IH
(min), t
CC
=
35
35
mA
No Input Change
Active Standby Current in Non-Power Down Mode
I
CC
3
P
CKE
V
IL
(max), t
CC
= 15ns
12
12
mA
I
CC
3
PS
CKE
V
IL
(max), t
CC
=
12
12
mA
I
CC
2
N
CKE = V
IH
, t
CC
= 15ns
30
30
mA
Active Standby Current in Power Down Mode
Input Change every 30ns
I
CC
2
NS
CKE
V
IH
(min), t
CC
=
, No Input Change
20
20
mA
Refresh Current
I
CC
5
t
RC
t
RC
(min)
210
210
mA
2
Self Refresh Current
I
CC
6
CKE
0.2V
3
3
mA
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
4
White Electronic Designs Corporation Westborough, MA (508) 366-5151
White Electronic Designs
EDI416S4030A
Parameter
Symbol
-10
-12
Units Notes
Min
Max
Min
Max
Clock Cycle Time
CAS latency = 3
t
CC
10
1000
12
1000
ns
1
CAS latency = 2
13
1000
15
1000
Clock to Valid Output Delay
t
SAC
7
8
ns
1, 2
Output Data Hold Time
t
OH
3
3
ns
2
Clock High Pulse Width
t
CH
3.5
4.0
ns
3
Clock Low Pulse Width
t
CL
3.5
4.0
ns
3
Input Setup Time
t
SS
2.5
3
ns
3
Input Hold Time
t
SH
1
1
ns
3
Clock to Output in Low-Z
t
SLZ
1
1
ns
2
Clock to Output in High-Z
t
SHZ
7
8
ns
Row Active to Row Active Delay
t
RRD
20
24
ns
4
RAS to CAS Delay
t
RCD
24
26
ns
4
Row Precharge Time
t
RP
24
26
ns
4
Row Active Time
t
RAS
50
100,000
60
100,000
ns
4
Row Cycle Time - Operation
t
RC
80
90
ns
4
Row Cycle Time - Auto Refresh
t
RFC
80
90
ns
4, 8
Last Data In to New Column Address Delay
t
CDL
1
1
CLK
5
Last Data In to Row Precharge
t
RDL
1
1
CLK
5
Last Data In to Burst Stop
t
BDL
1
1
CLK
5
Column Address to Column Address Delay
t
CCD
1
1
CLK
6
Number of Valid Output Data
CAS latency = 3
2
2
ea
7
CAS latency = 2
1
1
AC CHARACTERISTICS
O
PERATING
AC P
ARAMETIERS
(V
CC
= 3.0V
TO
3.6V, T
A
= -40C
TO
+85C)
NOTES:
1. Parameters depend on programmed CAS latency.
2. If clock rise time is longer than 1ns, (trise/2 - 0.5ns) should be added to the parameter.
3. Assumed input rise and fall time = 1ns. If trise & tfall are longer than 1ns, [(trise + tfall)/2]-1ns should be added to the parameter.
4. The minimum number of clock cycles required is determined by dividing the minimum time required by the clock cycle time and then rounding up to the
next higher integer.
5. Minimum delay is required to complete write.
6. All devices allow every cycle column address changes.
7. In case of row precharge interrupt, auto precharge and read burst stop.
8. A new command may be given tRFC after self refresh exit.
R
EFRESH
C
YCLE
P
ARAMETERS
-10
-12
Parameter
Symbol
Min
Max
Min
Max
Units
Notes
Refresh Period
t
REF
--
64
--
64
ms
1, 2
Self Refresh Exit Time
t
SREX
t
RFC
--
tRFC
--
ns
3
NOTES:
1. 4096 cycles.
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device.
3. The self refresh is exited by restarting the external clock and then asserting CKE high. This must be followed by NOPs for a minimum time of t
RFC
before the SDRAM
reaches idle state to begin normal operation.
5
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
EDI416S4030A
C
LOCK
F
REQUENCY
A
ND
L
ATENCY
P
ARAMETERS
- 100MH
Z
(U
NITS
=
NUMBER
OF
CLOCKS
)
Frequency
CAS
t
RC
t
RAS
t
RP
t
RRD
t
RCD
t
CCD
t
CDL
t
RDL
Latency
80ns
50ns
24ns
20ns
24ns
10ns
10ns
10ns
100MHz (10ns)
3
8
5
3
2
3
1
1
1
83MHz (12ns)
3
7
5
2
2
2
1
1
1
75MHz (12ns)
2
6
4
2
2
2
1
1
1
66MHz (15ns)
2
6
4
2
2
2
1
1
1
C
LOCK
F
REQUENCY
A
ND
L
ATENCY
P
ARAMETERS
- 83MH
Z
(U
NITS
=
NUMBER
OF
CLOCKS
)
Frequency
CAS
t
RC
t
RAS
t
RP
t
RRD
t
RCD
t
CCD
t
CDL
t
RDL
Latency
90ns
60ns
26ns
24ns
26ns
12ns
12ns
12ns
83MHz (12ns)
3
8
5
3
2
3
1
1
1
75MHz (13ns)
3
7
5
2
2
2
1
1
1
66MHz (15ns)
2
6
4
2
2
2
1
1
1
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