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Datasheet: EDI2CG472256V-9 (White Electronic Designs Corporation)

Organization = 4x256Kx72 ; Speed (ns) = 9-12 ; Volt = 3.3 ; Package = 168 Dimm ; Temp = C ;

 

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White Electronic Designs Corporation
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI2CG472256V
August 1998 Rev. 1
ECO #10656
4x256Kx72, 3.3V Synchronous/Synchronous Burst Flow-Through
FEATURES
s 4x256Kx72 Synchronous, Synchronous Burst
s Flow-Through Architecture
s Linear and Sequential Burst Support via MODE pin
s Clock Controlled Registered Module Enable (EM\)
s Clock Controlled Registered Bank Enables (E
1
\, E
2
\, E
3
\, E
4
\)
s Clock Controlled Byte Write Mode Enable (BWE\)
s Clock Controlled Byte Write Enables (BW
1
\ - BW
8
\)
s Clock Controlled Registered Address
s Clock Controlled Registered Global Write (GW\)
s Aysnchronous Output Enable (G\)
s Internally self-timed Write
s Individual Bank Sleep Mode enables (ZZ
1
, ZZ
2
, ZZ
3
, ZZ
4
)
s Gold Lead Finish
s 3.3V
10%, - 5% Operation
s Access Speed(s): t
KHQV
= 9, 10, 12, 15ns
s Common Data I/O
s High Capacitance (30pF) drive, at rated Access Speed
s Single total array Clock
s Multiple Vcc and Gnd
The EDI2CG472256VxxD2 is a Synchronous/Synchronous Burst
SRAM, 84 position Dual Key; Double High DIMM (168 contacts)
Module, organized as 4x256Kx72. The Module contains sixteen
(16) Synchronous Burst Ram Devices, packaged in the industry
standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4
Substrate. The module architecture is defined as a Sync/Sync
Burst, Flow-Through, with support for either linear or sequential
burst. This module provides High Performance, 2-1-1-1 accesses
when used in Burst Mode, and used as a Synchronous Only Mode,
provides a high performance cost advantage over BiCMOS
aysnchronous device architectures.
Synchronous Only operations are performed via strapping ADSC\
Low, and ADSP\ / ADV\ High, which provides for Ultra Fast
Accesses in Read Mode while providing for internally self-timed
Early Writes.
Synchronous/Synchronous Burst operations are in relation to an
externally supplied clock, Registered Address, Registered Global
Write, Registered Enables as well as an Asynchronous Output
enable. This Module has been defined with full flexibility, which
allows individual control of each of the eight bytes, as well as
Quad Words in both Read and Write Operations.
2
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI2CG472256V
PIN CONFIGURATION
DQ
0-63
Input/Output Bus
DQP
0-7
Parity Bits
A
0-17
Address Bus
EM\
Address Enable
E
1
\, E
2
\,
Synchronous Bank Enables
E
3
\, E
4
\
BWE\
Byte Write Mode Enable
BW
1
-
8
\
Byte Write Enables
CLK
Array Clock
GW\
Synchronous Global Write
Enable
G\
Asynchronous Output Enable
ZZ
1
, ZZ
2
,
Synchronous Bank Enables
ZZ
3
, ZZ
4
Vcc
3.3V Power Supply
Vss
Ground
NC
No Connect
PIN NAMES
PIN SYMBOLS
PIN
PIN
PIN
PIN
FRONT
FRONT
BACK
BACK
V
SS
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
A
16
A
14
A
12
A
10
V
CC
NC
V
SS
MODE
NC
1
V
CC
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
V
SS
A
17
A
15
V
CC
A
11
V
SS
NC
3
V
SS
CLK
V
SS
BWE\
V
CC
V
SS
DQ
19
V
SS
DQ
24
DQ
25
DQP
2
V
SS
DQ
31
DQ
30
V
SS
NC
2
V
CC
A
13
DQ
20
A
0
A
2
A
4
A
6
A
1
A
3
A
5
A
7
NC
4
V
CC
DQ
16
DQ
23
DQ
22
DQ
17
DQ
18
DQ
21
V
CC
DQP
3
V
CC
A
8
BW
8
\
BW
7
\
V
SS
A
9
BW
6
\
BW
5
\
V
SS
ZZ
2
E
4
\
E
2
\
EM\
GW\
BW
4
\
BW
3
\
ADSC\
ADSP\
E
1
\
E
3
\
G\
BW
2
\
BW
1
\
ADV\
DQ
26
DQ
27
V
SS
NC
5
V
CC
DQ
32
DQ
33
DQ
34
DQ
35
V
SS
V
CC
DQ
40
DQ
41
DQ
42
DQ
43
V
SS
DQ
29
DQ
28
V
SS
DQP
4
V
CC
DQ
39
DQ
38
DQ
37
DQ
36
V
SS
DQP
5
V
CC
DQ
47
DQ
46
DQ
45
10
11
12
13
14
15
16
17
18
DQ
44
V
SS
V
CC
DQ
0
DQ
1
DQ
2
DQ
3
V
SS
V
CC
DQ
8
DQ
9
DQ
10
DQ
11
V
SS
DQP
0
V
CC
DQ
7
DQ
6
DQ
5
DQ
4
V
SS
DQP
1
V
CC
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
NC
6
V
CC
DQ
48
DQ
49
DQ
50
DQ
51
V
SS
V
CC
DQ
56
DQ
57
DQ
58
DQ
59
V
SS
DQP
6
V
CC
DQ
55
DQ
54
DQ
53
DQ
52
V
SS
DQP
7
V
CC
DQ
63
DQ
62
DQ
61
DQ
60
V
SS
ZZ
3
ZZ
1
ZZ
4
1
2
3
4
5
6
7
8
9
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI2CG472256V
FUNCTIONAL BLOCK DIAGRAM
ADV\
A
0-17
ADSP\
ADSC\
CLK
EM\
E
1
\
G \
GW\
MODE
ZZ
1
BW
1
\
BW
2
\
DQP
0
DQP
1
DQ
0-15
U1
U5
U9
ZZ
3
ZZ
4
ZZ
2
E
2
\
E
3
\
E
4
\
BW
3
\
BW
4
\
DQP
2
DQP
3
U2
U6
BW
5
\
BW
6
\
DQP
4
DQP
5
U3
U7
BW
7
\
BW
8
\
DQP
6
DQP
7
U4
U8
U13
U10
U14
U11
U15
U12
U16
DQ
48-63
DQ
32-47
DQ
16-31
4
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI2CG472256V
PIN DESCRIPTIONS
DIMM Pins
Symbol
Type
Description
2, 87, 4, 89, 7, 92
A
0-17
Input
Addresses: These inputs are registered and must meet the setup and hold times around the rising
9, 94, 12, 96, 10
Synchronous
edgeof CLK. The burst counter generates internal addresses associated with A
0
and A
1
, during burst
93, 8, 91, 5, 88,
and wait cycle.
3, 86
107, 106, 23,
BW
1
\, BW
2
\,
Input
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle. BW
0
/ controls DQ
0-7
22, 109, 108,
BW
3
\, BW
4
\,
Synchronous
and DQP
0
, BW
1
\ controls DQ
8-15
and DQP
1
. BW
2
\ controls DQ
16-23
and DQP
2
. BW
3
\ controls DQ
24-31
25, 24
BW
5
\, BW
6
\,
and DQP
3
. BW
4
\ controls DQ
32-39
and DQP
4
. BW5\ controls DQ
40-47
and BW
6
\ controls DQ
48-55
and
BW
7
\, BW
8
\
DQP6. BW7\ controls DQ56-64 and DQP7.
104
BWE\
Input
Write Enable: This active LOW input gates byte write operations and must meet the setup and hold
Synchronous
times around the rising edge of CLK.
19
GW\
Input
Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the BWE\ and
Synchronous
BWx\ lines and must meet the setup and hold times around the rising edge of CLK.
101
CLK
Input
Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on
Synchronous
its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge.
98, 15,
E
1
\, E
2
\
Input
Bank Enables: These active LOW inputs are used to enable each individual bank and to gate ADSP\.
99,14
E
3
\, E
4
\
Synchronous
103
G\
Input
Output Enable: This active LOW asynchronous input enables the data output drivers.
111
ADV\
Input
Address Status Processor: This active LOW input is used to control the
Synchronous
internal burst counter. A HIGH on this pin generates wait cycle (no address advance).
27
ADSP\
Input
Address Status Processor: This active LOW input, along with EL\ and EH\ being LOW, causes a
Synchronous
new external address to be registered and a READ cycle is initiated using the new address.
26
ADSC\
Input
Address Status Controller: This active LOW input causes device to be deselected or selected along
Synchronous
with new external address to be registered. A READ or WRITE cycle is initiated depending upon write
control inputs.
17
MODE
Input Static
Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or
HIGH on this pin selects INTERLEAVED BURST.
36, 50,
ZZ
1
, ZZ
2
,
Input
Snooze: These active HIGH inputs put the individual banks in low power consumption standby mode.
64, 78
ZZ
3
, ZZ
4
Asynchronous
For normal operation, this input has to be either LOW or NC (no connect).
Various
DQ
0-63
Input/Output
Data Inputs/Outputs: First byte is DQ
0-7
, second byte is DQ
8-15
, third byte is DQ
16-23
, fourth byte is
DQ
24-31
, fifth byte is DQ
32-39
, sixth byte is DQ
40-47
, seventh byte is DQ
48-55
and the eight byte is DQ
56-64
.
113, 120, 127,
DQP
0-7
Input/Output
Parity Inputs/Outputs: DQP
0
is parity bit for DQ
0-7
. DQP
1
is parity bit for DQ
8-15
. DQP
2
is parity bit
134, 141, 148,
for DQ
16-23
. DQP
3
is parity bit for DQ
24-31
. DQP
4
\ is parity bit for DQ
32-39
. DQP
5
is parity bit for
155, 162
DQ
40-47
. DQP6\ is parity bit for DQ
48-55
. DQP
7
is parity bit for DQ
56-64
and DQP
7
. In order to use the
device configured as a 128K x 64, the parity bits need to be tied to Vss through a 10K ohm resistor.
Various
Vcc
Supply
Power supply: +3.3V -5%/+10%
Various
Vss
Ground
Ground
5
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI2CG472256V
SYNCHRONOUS BURST - TRUTH TABLE
Operation
E1\
E2\
E3\
E4\ ADSP\ ADSC\
ADV\
GW\
G\
CLK
DQ
Addr. Used
Deselected Cycle, Power Down; Bank 1
H
X
*
*
X
L
X
X
X
L-H
High-Z
None
Deselected Cycle, Power Down; Bank 2
X
H
*
*
X
L
X
X
X
L-H
High-Z
None
Read Cycle, Begin Burst; Bank 1
L
H
*
*
L
X
X
X
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
*
*
L
X
X
X
H
L-H
High-Z
External
Read Cycle, Begin Burst; Bank 2
H
L
*
*
L
X
X
X
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
*
*
L
X
X
X
H
L-H
High-Z
External
Write Cycle, Begin Burst; Bank 1
L
H
*
*
H
L
X
L
X
L-H
D
External
Write Cycle, Begin Burst; Bank 2
H
L
*
*
H
L
X
L
X
L-H
D
External
Read Cycle, Begin Burst; Bank 1
L
H
*
*
H
L
X
H
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
*
*
H
L
X
H
H
L-H
High-Z
External
Read Cycle, Begin Burst; Bank 2
H
L
*
*
H
L
X
H
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
*
*
H
L
X
H
H
L-H
High-Z
External
Read Cycle, Continue Burst; Bank 1
X
H
*
*
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
X
H
*
*
X
H
L
H
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
X
*
*
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
X
*
*
X
H
L
H
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 1
H
H
*
*
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
H
H
*
*
X
H
L
H
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
H
*
*
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
H
*
*
X
H
L
H
H
L-H
High-Z
Next
Write Cycle, Continue Burst; Bank 1
X
H
*
*
H
H
L
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 1
H
H
*
*
X
H
L
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
X
*
*
H
H
L
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
H
*
*
X
H
L
L
X
L-H
D
Next
Read Cycle, Suspend Burst; Bank 1
X
H
*
*
H
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
X
H
*
*
H
H
H
H
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 2
H
X
*
*
H
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
X
*
*
H
H
H
H
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 1
H
H
*
*
X
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
H
H
*
*
X
H
H
H
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 2
H
H
*
*
X
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
H
*
*
X
H
H
H
H
L-H
High-Z
Current
Write Cycle, Suspend Burst; Bank 1
X
H
*
*
H
H
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 1
H
H
*
*
X
H
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
X
*
*
H
H
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
H
*
*
X
H
H
L
X
L-H
D
Current
*All Truth Table Functions Repeat for Bank 3 (E
3
\) and Bank 4 (E
4
\)
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