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Datasheet: W65C265S (Western Design Center)

The WDC W65C265S Microcomputer isA Complete Fully Static 16-bit Computer Fabricated on...

 

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WESTERN DESIGN CENTER
W65C265S
March 1, 2000
W65C265S DATA SHEET
WESTERN DESIGN CENTER
W65C265S
March 1, 2000
WDC reserves the right to make changes at any time without
notice in order to improve design and supply the best possible
product. Information contained herein is provided gratuitously
and without liability, to any user. Reasonable efforts have been
made to verify the accuracy of the information but no
guarantee whatsoever is given as to the accuracy or as to its
applicability to particular uses. In every instance, it must be the
responsibility of the user to determine the suitability of the
products for each application. WDC products are not
authorized for use as critical components in life support devices
or systems. Nothing contained herein shall be construed as a
recommendation to use any product in violation of existing
patents or other rights of third parties. The sale of any WDC
product is subject to all WDC Terms and Conditions of Sales
and Sales Policies, copies of which are available upon request.
Copyright (C) 1981-2001The Western Design Center, Inc. All
rights reserved, including the right of reproduction in whole or
in part in any form.
WESTERN DESIGN CENTER
W65C265S
March 1, 2000
TABLE OF CONTENTS
INTRODUCTION
1
SECTION 1 W65C265S FUNCTION DESCRIPTION
2
1.1
The W65C816S Static 16-bit Microprocessor Core
2
1.2
8K x 8 ROM
2
1.3
576 x 8 RAM
2
1.4
Bus Control Register
2
Table 1-1 BCR7 and BE Control
3
Figure 1-1 BE Timing Relative to RESB Input
3
Figure 1-2 Bus Control Register
4
1.5
The Timers
5
Table 1-2 The Timer Functions
5
Figure 1-3 Timer Control Register
6
Figure 1-4 Timer Enable Register
6
1.6
Interrupt Flag Registers
7
1.7
Interrupt Enable Registers
7
Figure 1-5 Timer Interrupt Enable Register and Timer Interrupt Flag Register
8
Figure 1-6 Edge Interrupt Enable Register and Edge Interrupt Flag Register
8
Figure 1-7 UART Interrupt Enable Register and UART Interrupt Flag Reg.
9
1.8
Asynchronous I/O Data Rate Generation
10
1.9
Universal Asynchronous Receiver/Transmitters
11
Figure 1-8 Asynchronous Transmitter Mode with Parity
11
Figure 1-9 Asynchronous Data Timing for 7-bit Data without Parity
12
Figure 1-10 ACSRx Bit Assignments
13
1.10
The Parallel Interface Bus
14
Figure 1-11 The PIB Registers
14
Figure 1-12 Parallel Interface Bus Enable and Flag Registers
15
1.11
Twin Tone Generators
16
Figure 1-13 Tone Generator Block Diagram
16
Table 1-4 Comm. Freq. Generated by the Tone Generator Timers 5 and 6
17
1.12
Processor Defined Cache Control
18
Figure 1-14 System Speed Control Register
18
Figure 1-15 System Speed Change Timing Diagram
19
1.13
Programming Model and Memory Map
20
Figure 1-16 W65C816S Programming Model and Memory Map
20
Table 1-5 System Memory Map
21
Table 1-6A I/O Register Memory Map
22
Table 1-6B Control and Status Register Memory Map
23
Table 1-6C Timer Register Memory Map
24
Table 1-6D Communication Register Memory Map
25
Table 1-7A Emulation Mode Vector Table
26
Table 1-7B Native Mode Vector Table
27
Table 1-8A W65C265S 84 Lead Pin Map
28
WESTERN DESIGN CENTER
W65C265S
March 1, 2000
SECTION 2 PIN FUNCTION DESCRIPTION
31
Figure 2-1 W65C265S Interface Diagram
31
Figure 2-2 W65C265S 84 Lead Chip Carrier Pinout
32
Figure 2-3 W65C265S 100 Lead Quad Flat Pack Pinout
33
2.1
Write Enable
34
2.2
RUN and SYNC outputs with WAI and STP defined
34
2.3
Phase 2 Clock Output
34
2.4
Clock Inputs
34
2.5
Bus Enable and RDY Input
35
Figure 2-5 BE Timing Relative to PHI2
35
2.6
Reset Input/Output
36
2.7
Positive Power Supply
36
2.8
Internal Logic Ground
36
2.9
I/O Port Pins
36
2.10
Address Bus
36
2.11
Data Bus
37
2.12
Positive Edge Interrupt inputs
37
2.13
Negative Edge Interrupt inputs
37
2.14
Chip Select outputs
37
2.15
Level Sensitive Interrupt Request input
37
2.16
Non-Maskable Edge and ABORT Interrupt Input
37
2.17
Asynchronous Receiver Inputs/Transmitter Outputs
38
2.18
Timer 4 Input and Output
38
2.19
Bus Available/Disable Output Data
38
2.20
Tone Generator Outputs
38
2.21
Parallel Interface Bus
38
2.22
Pulse Width Measurement Input
39
SECTION 3 TIMING, AC AND DC CHARACTERISTICS
40
3.1
Absolute Maximum Ratings
40
Table 3-1 Absolute Maximum Ratings
40
3.2
DC Characteristics
41
Table 3-2 DC Characteristics
41
3.3
AC Characteristics
42
Table 3-3 AC Characteristics
42
3.4
AC Parameters
43
Table 3-4 AC Parameters
43
3.5
AC Timing Diagram Notes
44
3.6
AC Timing Diagrams
45
Figure 3-1 AC Timing Diagram #1
45
Figure 3-2 AC Timing Diagram #2
46
Figure 3-3 AC Timing Diagram #3
47
Figure 3-4 AC Timing Diagram #4
48
WESTERN DESIGN CENTER
W65C265S
March 1, 2000
SECTION 4 ORDERING INFORMATION
49
SECTION 5 APPLICATION INFORMATION
50
5.1
W65C265S Block Diagrams
50
Figure 5-1 W65C265S Block Diagram
51
Figure 5-2 W65C265S Interrupt Controller Block Diagram
52
Figure 5-3 W65C265S Timers 0-7 Block Diagram
53
Figure 5-4 W65C265S UART Block Diagram
54
Figure 5-5 W65C265S Parallel Interface Bus Diagram
55
Figure 5-6 W65C265S Tone Generator Block Diagram
56
5.2
W65C265DB Developer Board
57
Figure 5-7 W65C265DB Developer Board
57
5.3
External ROM Startup with W65C265S Mask ROM
59
5.4
Recommended clock and fclock Oscillators
60
Figure 5-8 Oscillator Circuit
60
Figure 5-9 Circuit Board Layout for Oscillator
61
Figure 5-10 Resonator Circuit
62
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