HTML datasheet архив (поиск документации на электронные компоненты) Поиск даташита (1.687.043 компонентов)
Где искать

Datasheet: W65C134S (Western Design Center)

 

Скачать: PDF   ZIP
 
WESTERN DESIGN CENTER
W65C134S
March 1, 2000
W65C134S DATA SHEET
WESTERN DESIGN CENTER
W65C134S
March 1, 2000
WDC reserves the right to make changes at any time without notice in
order to improve design and supply the best possible product.
Information contained herein is provided gratuitously and without
liability, to any user. Reasonable efforts have been made to verify the
accuracy of the information but no guarantee whatsoever is given as to
the accuracy or as to its applicability to particular uses. In every instance,
it must be the responsibility of the user to determine the suitability of the
products for each application. WDC products are not authorized for use
as critical components in life support devices or systems. Nothing
contained herein shall be construed as a recommendation to use any
product in violation of existing patents or other rights of third parties.
The sale of any WDC product is subject to all WDC Terms and
Conditions of Sales and Sales Policies, copies of which are available upon
request.
Copyright (C) 1981-20001by The Western Design Center, Inc. All rights
reserved, including the right of reproduction in whole or in part in any
form.
WESTERN DESIGN CENTER
W65C134S
March 1, 2000
TABLE OF CONTENTS
INTRODUCTION ............................................................................................................................................... 1
SECTION 1 W65C134S FUNCTION DESCRIPTION......................................................................................... 2
1.1
The W65C02S Static 8-bit Microprocessor Core ....................................................................... 2
1.2
4096 x 8 ROM.......................................................................................................................... 2
1.3
192 x 8 RAM............................................................................................................................ 2
1.4
Bus Control Register ................................................................................................................. 2
Table 1-1 BCR7 and BE Control .............................................................................................. 2
Figure 1-1 BE Timing Relative to RESB Input ......................................................................... 3
Figure 1-2 Bus Control Register ............................................................................................... 3
1.5
Chip Select Enable Register ...................................................................................................... 4
Figure 1-3 Chip Select Enable Register..................................................................................... 4
1.6
The Timers................................................................................................................................ 4
Figure 1-3 Timer Control Register One..................................................................................... 5
Figure 1-4 Timer Control Register Two ................................................................................... 6
1.7
Interrupt Flag Registers ............................................................................................................. 7
1.8
Interrupt Enable Registers ......................................................................................................... 7
Figure 1-5 Interrupt Enable Register One and Interrupt Flag Register One................................. 8
Figure 1-6 Interrupt Enable Register Two and Interrupt Flag Register Two ............................... 9
1.9
Asynchronous I/O Data Rate Generation .................................................................................. 10
Table 1-2 Timer A Values for Baud Rate Selection.................................................................. 10
1.10
Universal Asynchronous Receiver/Transmitter .......................................................................... 11
Figure 1-7 Asynchronous Transmitter Mode with Parity .......................................................... 11
Figure 1-8 Asynchronous Receiver Data Timing ...................................................................... 12
Figure 1-9 ACSR Bit Assignments .......................................................................................... 13
1.11
The Serial Interface Bus ........................................................................................................... 14
Figure 1-10 SIB State Register ................................................................................................ 14
Figure 1-11 SR0, SR1, SR2, and SR3 Shift Register ................................................................ 15
Figure 1-12 SIB Control and Status Register ........................................................................... 16
Figure 1-13 Serial Interface Bus Message Transmission Timing Diagram ................................ 19
Figure 1-14 W65C134S Serial Interface Bus Wiring Diagram ................................................. 20
Figure 1-15 Bus Address Register............................................................................................ 20
1.12
Programming Model, Status Register Coding and Memory Map................................................ 21
Figure 1-16 W65C02S Microprocessor Programming Model ................................................... 21
Figure 1-17 W65C02S Status Register Coding ........................................................................ 21
Table 1-3 System Memory Map .............................................................................................. 22
Table 1-4 I/O Memory Map .................................................................................................... 23
Table 1-5 Vector Table ........................................................................................................... 24
Table 1-6 W65C134S 68 Lead Pin Map .................................................................................. 25
SECTION 2 PIN FUNCTION DESCRIPTION
27
Figure 2-1 W65C134S Interface Diagram................................................................................ 27
Figure 2-2 W65C134S 68 Lead Chip Carrier Pinout................................................................ 28
Figure 2-3 W65C134S 80 Lead Quad Flat Pack Pinout ........................................................... 29
2.1
WEB Write Enable................................................................................................................... 30
2.2
RUN and SYNC ...................................................................................................................... 30
WESTERN DESIGN CENTER
W65C134S
March 1, 2000
2.3
Phase 2 Clock Output............................................................................................................... 30
2.4
Clock Inputs, Clock Outputs..................................................................................................... 30
2.5
Bus Enable and RDY Input ..................................................................................................... 31
Figure 2-3 BE Timing Relative to PHI2 ................................................................................... 31
2.6
Reset Input/Output RESB ........................................................................................................ 32
2.7
Positive Power Supply.............................................................................................................. 32
2.8
Internal Logic Ground .............................................................................................................. 32
2.9
I/O Port Pins ............................................................................................................................ 32
2.10
Address Bus............................................................................................................................. 33
2.11
Data Bus.................................................................................................................................. 33
2.12
Positive Edge Interrupt inputs................................................................................................... 33
2.13
Negative Edge Interrupt inputs ................................................................................................. 33
2.14
Chip Select outputs .................................................................................................................. 33
2.15
Level Sensitive Interrupt Request inputs ................................................................................... 34
2.16
Non-Maskable Edge Interrupt Input.......................................................................................... 34
2.17
Asynchronous Receive Input/Transmitter Output ...................................................................... 34
2.18
Timer A Input and Output ........................................................................................................ 34
2.19
The Serial Interface Bus pins.................................................................................................... 34
SECTION 3 TIMING, AC AND DC CHARACTERISTICS ................................................................................... 35
3.1
Absolute Maximum Ratings ..................................................................................................... 35
Table 3-1 Absolute Maximum Ratings..................................................................................... 35
3.2
DC Characteristics ................................................................................................................... 36
Table 3-2 DC Characteristics .................................................................................................. 36
3.3
AC Characteristics ................................................................................................................... 37
Table 3-3 AC Characteristics .................................................................................................. 37
3.4
AC Parameters......................................................................................................................... 38
Table 3-4 AC Parameters ........................................................................................................ 38
3.5
AC Timing Diagram Notes....................................................................................................... 39
3.6
AC Timing Diagrams ............................................................................................................... 40
Figure 3-1 AC Timing Diagram #1.......................................................................................... 40
Figure 3-2 AC Timing Diagram #2.......................................................................................... 41
Figure 3-3 AC Timing Diagram #3.......................................................................................... 42
Figure 3-4 AC Timing Diagram #4.......................................................................................... 43
Figure 3-5 AC Timing Diagram #5.......................................................................................... 44
SECTION 4 ORDERING INFORMATION......................................................................................................... 45
SECTION 5 APPLICATION INFORMATION .................................................................................................... 46
5.1
W65C134S Block Diagrams..................................................................................................... 46
Figure 5-1 W65C134S Block Diagram .................................................................................... 46
Figure 5-2 W65C134S Interrupt Controller Block Diagram ..................................................... 47
Figure 5-3 W65C134S Timer 1 and 2 Block Diagram.............................................................. 48
Figure 5-4 W65C134S Timer A and M Block Diagram ........................................................... 49
Figure 5-5 Universal Asynchronous Receiver Transmitter Block Diagram ................................ 50
Figure 5-6 Serial Interface Bus Block Diagram ........................................................................ 51
5.2
External ROM Startup with W65C134S Mask ROMs .............................................................. 52
5.3
Recommended clock and fclock oscillators................................................................................ 53
Figure 5-7 Oscillator Circuit..................................................................................................... 53
Figure 5-8 Circuit Board Layout for Oscillator Circuit............................................................. 54
WESTERN DESIGN CENTER
W65C134S
March 1, 2000
Figure 5-9 W65C134S Resonator Circuit ................................................................................ 55
5.4
Wait state information and uses for the BE pin.......................................................................... 55
5.5
Figure 5-10 W65C134SPCB Embedded System Development Board Block Diagram ............... 56
© 2017 • ChipFind
Контакты
Главная страница