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Datasheet: VT6516 (VIA Tech.)

16/12-port 10/100base-T/TX Ethernet Switch Controller

 

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VIA Technologies, Inc.
Preliminary VT6516 Datasheet
1
VT6516
16/12-P
ORT
10/100B
ASE
-T/TX
E
THERNET
S
WITCH
C
ONTROLLER
REVISION `E' DATASHEET
(Preliminary)
ISSUE 1: July 31, 1999
VIA Technologies, Inc.
VIA Technologies, Inc.
Preliminary VT6516 Datasheet
2
P
RELIMINARY
R
ELEASE
Please contact VIA Technologies for the latest documentation.
Copyright Notice:
Copyright 1995, VIA Technologies Incorporated. Printed in Taiwan. A
LL
R
IGHTS
R
ESERVED
.
No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval
system, or translated into any language, in any form or by any means, electronic, mechanical,
magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA
Technologies Incorporated.
The VT86C100P may only be used to identify products of VIA Technologies.
All trademarks are the properties of their respective owners.
Disclaimer Notice:
No license is granted, implied or otherwise, under any patent or patent rights of VIA
Technologies. VIA Technologies makes no warranties, implied or otherwise, in regard to this
document and to the products described in this document. The information provided by this
document is believed to be accurate and reliable to the publication date of this document.
However, VIA Technologies assumes no responsibility for any errors in this document.
Furthermore, VIA Technologies assumes no responsibility for the use or misuse of the
information in this document and for any patent infringements that may arise from the use of
this document. The information and product specifications within this document are subject to
change at any time, without notice and without obligation to notify any person of such change.
Offices:
1045 Mission Court
8
th
Floor, No. 533
Fremont, CA 94539
Chung-Cheng Rd., Hsin-Tien
USA
Taipei, Taiwan ROC
Tel:
(510) 683-3300
Tel:
(886-2) 2218-5452
Fax:
(510) 683-3301
Fax:
(886-2) 2218-5453
Online Services:
BBS : 886-2-2186408
FTP :
FTP.VIA.COM.TW
HTTP:
WWW.VIA.COM.TW
or-
WWW.VIATECH.COM
VIA Technologies, Inc.
Preliminary VT6516 Datasheet
3
T
ABLE OF
C
ONTENTS
T
ABLE OF
C
ONTENTS
................................................................................................................................ 3
F
IGURES AND
T
ABLES
............................................................................................................................... 4
R
EVERSION
H
ISTORY
................................................................................................................................ 5
F
EATURES
................................................................................................................................................ 6
B
LOCK
D
IAGRAM
...................................................................................................................................... 9
B
ALL OUT
D
IAGRAM
............................................................................................................................... 11
RMII-mode Ball out Diagram ........................................................................................................... 11
MII-mode Ballout Diagram............................................................................................................... 12
L
OGIC
S
YMBOL
...................................................................................................................................... 13
P
IN
D
ESCRIPTIONS
.................................................................................................................................. 14
J
UMPER
S
TRAPPING
................................................................................................................................. 18
SECTION I FUNCTIONAL DESCRIPTIONS...................................................................................... 19
1. G
ENERAL
D
ESCRIPTION
...................................................................................................................... 19
2. T
HE
VIA E
THER
S
WITCH
A
RCHITECTURE
............................................................................................ 19
2.1 Switch initialization procedures .................................................................................................. 19
2.2 Packet receiving and forwarding follow .......................................
~
! |
w q
C
3. I
NTERFACE
D
ESCRIPTIONS
................................................................................................................... 20
3.1 Buffer Memory (SDRAM) Interface and Table (SRAM) interface..
~
! |
w q
C
4. F
UNCTIONAL
D
ESCRIPTION
................................................................................................................. 33
4.1 Packet Reception and Address recognition.................................................................................. 33
4.2 Packet Forwarding and VLAN..................................................................................................... 33
4.3 Network Management Features................................................................................................... 34
SECTION II REGISTER MAP............................................................................................................... 36
1. R
EGISTER
T
ABLES
............................................................................................................................. 36
2 CPU I
NTERFACE
R
EGISTERS
M
AP
......................................................................................................... 36
3 S
WITCH
I
NTERNAL
R
EGISTERS
M
AP
..................................................................................................... 37
4. D
ETAIL OF
S
WITCH
R
EGISTER
.............................................................................................................. 44
4.1 Registers of SDRAM Control Module......................................................................................... 44
4.2 Registers of SRAM Control Module............................................................................................ 46
4.4 Registers of Buffer Control Module............................................................................................. 48
4.5 Registers of Forwarding Control Module ................................................................................... 49
4.6 Registers of PHY Control Module .............................................................................................. 53
4.7 Registers of EEPROM Control Module ....................................................................................... 55
4.8 Registers of CPU Interface Module............................................................................................. 56
4.9 Registers of MAC/IO Control Module ......................................................................................... 59
4.10 Registers of CPU IO Control Module....................................................................................... 63
SECTION III ELECTRICAL SPECIFICATIONS................................................................................. 65
A
BSOLUTE
M
AXIMUM
R
ATINGS
............................................................................................................... 65
DC C
HARACTERISTICS
............................................................................................................................ 65
AC C
HARACTERISTICS
............................................................................................................................ 65
P
ACKAGE
M
ECHANICAL
S
PECIFICATIONS
................................................................................................. 73
VIA Technologies, Inc.
Preliminary VT6516 Datasheet
4
F
IGURES AND
T
ABLES
Figure 1: Block Diagram .............................................................................................9
Figure 3-3 .................................................................................................................22
Figure 3-6: Algorithm of Initialization of Free Link Lists. ..........................................22
Figure 3-1 SRAM......................................................................................................26
Figure 3-2 Free buffer link structure ..........................................................................27
Table 1-0 Free buffer link structure............................................................................27
Figure 3-5 The Address table entries structure +........................................................27
Table 1-1 Address table structure ..............................................................................28
Table 3-1 RMII interface signals................................................................................30
Figure 3-1 RMII timing diagram ................................................................................30
Table 3-2 MII interface signals ..................................................................................31
Figure 3-2 MII timing diagram ..................................................................................31
VIA Technologies, Inc.
Preliminary VT6516 Datasheet
5
R
EVERSION
H
ISTORY
Reversion
Date
Reason for change
By
V0.90
2/18/1999
First release version
JeffreyChang
V0.91
6/2/1999
Add D version silicon features
modification
JeffreyChang
V0.92
8/23/1999
Add E version silicon features
modification
MurphyChen
V0.93
9/9/1999
Revision according to Weipin's,
Kevin's, and Ruth's comments
MurphyChen
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