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Datasheet: 24C04 (Turbo IC, Inc.)

 

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CMOS IC 2-WIRE BUS
4K ELECTRICALLY ERASABLE PROGRAMMABLE ROM
512 X 8 BIT EEPROM
Turbo IC, Inc.
24C04
PRODUCT INTRODUCTION
PIN DESCRIPTION
DESCRIPTION:
The Turbo IC 24C04 is a serial 4K EEPROM fabricated with
Turbo's proprietary, high reliability, high performance CMOS
technology. It's 4K of memory is organized as 512 x 8 bits.
The memory is configured as 32 pages with each page con-
taining 16 bytes. This device offers significant advantages
in low power applications.
The Turbo IC 24C04 uses the IC addressing protocol and
2-wire serial interface which includes a bidirectional serial
data bus synchronized by a clock. It offers a flexible byte
write and a faster 16-byte page write.
The Turbo IC 24C04 is assembled in either a 8-pin PDIP or
8-pin SOIC package. Pin #1 is not connected (NC). Pin #2
is the A1 device address input for the 24C04. Pin #3 is the
A2 device address input for the 24C04, such that a total of
four 24C04 devices can be connected on a single bus. Pin
#4 is the ground (Vss). Pin #5 is the serial data (SDA) pin
used for bidirectional transfer of data. Pin #6 is the serial
clock (SCL) input pin. Pin #7 is the write protect (WP) pin
used to protect hardware data. Pin #8 is the power supply
(Vcc) pin.
All data is serially transmitted in bytes (8 bits) on the SDA
bus. To access the Turbo IC 24C04 (slave) for a read or
write operation, the controller (master) issues a start condi-
tion by pulling SDA from high to low while SCL is high. The
master then issues the device address byte which consists
of 1010 (A2) (A1) (B8) (R/W). The most significant bits (1010)
are a device type code signifying an EEPROM device. A1
and A2 are the device address select bits which has to match
the A1 and A2 pin inputs on the 24C04 device. The B[8] bit
is the most significant bit of the memory address. The read/
write bit determines whether to do a read or write operation.
After each byte is transmitted, the receiver has to provide
an acknowledge by pulling the SDA bus low on the ninth
clock cycle. The acknowledge is a handshake signal to the
transmitter indicating a successful data transmission.
FEATURES :
Power Supply Voltage
Single Vcc for Read and Programming
(Vcc = 2.7 V to 5.5 V)
Low Power (Isb = 2a @ 5.5 V)
IC Bus, 2-Wire Serial Interface
Support Byte Write and Page Write (16 Bytes)
Automatic Page write Operation (maximum 10 ms)
Internal Control Timer
Internal Data Latches for 16 Bytes
High Reliability CMOS Technology with EEPROM Cell
Endurance : 1,000,000 Cycles
Data Retention : 100 Y
ears
1
SERIAL CLOCK (SCL)
The SCL input synchronizes the data on the SDA
bus. It is used in conjunction with SDA to define
the start and stop conditions. It is also used in
conjunction with SDA to transfer data to and from
the Turbo IC 24C04.
SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data
in and out of the Turbo IC 24C04. The pin is an
open-drain output. A pullup resistor must be con-
nected from SDA to Vcc.
PIN DESCRIPTION
DEVICE ADDRESS (A1 & A2)
A1 and A2 are device address inputs that en-
ables a total of four 24C04 devices to connect
on a single bus. When the address input pin is
left unconnected, it is interpreted as zero.
WRITE PROTECT (WP)
When the write protect input is connected to Vcc,
the entire memory array is protected against write
operations. For normal write operations, the write
protect pin should be grounded. When the pin is
left unconnected, WP is interpreted as zero.
1
2
3
4
5
6
7
8
NC
A1
A2
GND
VCC
WP
SCL
SDA
8 pin PDIP
1
2
3
4
5
6
7
8
NC
A1
A2
GND
VCC
WP
SCL
SDA
8 pin SOIC
24C04
PRODUCT INTRODUCTION
Turbo IC, Inc.
Note: The write cycle time t
WC
is the time from a valid stop condition of a write sequence to the end of the internal clear / write cycle.
DESCRIPTION (Continued):
For a write operation, the master issues a start condition, a
device address byte, a memory address byte, and then up to
16 data bytes. The Turbo IC 24C04 acknowledges after each
byte transmission. To terminate the transmission, the master
issues a stop condition by pulling SDA from low to high while
SCL is high.
For a read operation, the master issues a start condition and
a device address byte. The Turbo IC 24C04 acknowledges,
and then transmits a data byte, which is accessed from the
EEPROM memory. The master acknowledges, indicating that
it requires more data bytes. The Turbo IC 24C04 transmits
more data bytes, with the memory address counter auto-
matically incrementing for each data byte, until the master
does not acknowledge, indicating that it is terminating the
transmission. The master then issues a stop condition.
DEVICE OPERATION:
BIDIRECTIONAL BUS PROTOCOL:
The Turbo IC 24C04 follows the IC bus protocol. The proto-
col defines any device that sends data onto the SDA bus as
a transmitter, and the receiving device as a receiver. The
device controlling the transfer is the master and the device
being controlled is the slave. The master always initiates the
data transfers, and provides the clock for both transmit and
receive operations. The Turbo IC 24C04 acts as a slave de-
vice in all applications. Either the master or the slave can
take control of the SDA bus, depending on the requirement
of the protocol.
START/STOP CONDITION AND DATA TRANSITIONS:
While SCL clock is high, a high to low transition on the SDA
bus is recognized as a START condition which precedes any
read or write operation. While SCL clock is high, a low to
high transition on the SDA bus is recognized as a STOP con-
dition which terminates the communication and places the
Turbo IC 24C04 into standby mode. All other data transitions
on the SDA bus must occur while SCL clock is low to ensure
proper operation.
ACKNOWLEDGE:
All data is serially transmitted in bytes (8 bits) on the SDA
bus. The acknowledge protocol is used as a handshake sig-
nal to indicate successful transmission of a byte of data. The
bus transmitter, either the master or the slave (Turbo IC
24C04), releases the bus after sending a byte of data on the
SDA bus. The receiver pulls the SDA bus low during the ninth
clock cycle to acknowledge the successful transmission of a
byte of data. If the SDA is not pulled low during the ninth
clock cycle, the Turbo IC 24C04 terminates the data trans-
mission and goes into standby mode.
For the write operation, the Turbo IC 24C04 acknowledges
after the device address byte, acknowledges after the memory
address byte, and acknowledges after each subsequent data
byte.
For the read operation, the Turbo IC 24C04 acknowledges
after the device address byte. Then the Turbo IC 24C04 trans-
mits each subsequent data byte, and the master acknowl-
edges after each data byte transfer, indicating that it requires
more data bytes. The Turbo IC 24C04 monitors the SDA bus
for the acknowledge. To terminate the transmission, the mas-
ter does not acknowledge, and then sends a stop condition.
Write Cycle Timing
SCL
SDA
WORD n
8th BIT
ACK
STOP
CONDITION
START
CONDITION
t
WC
2
24C04
PRODUCT INTRODUCTION
Data Valid
Turbo IC, Inc.
Start and Stop Definition
Output Acknowledge
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
SDA
SCL
START
STOP
SCL
DATA IN
DATA OUT
1
8
9
ACKNOWLEDGE
START
3
24C04
PRODUCT INTRODUCTION
Turbo IC, Inc.
DEVICE ADDRESSING:
Following the start condition, the master will issue a device
address byte consisting of 1010 (A2) (A1) (B8) (R/W) to ac-
cess the selected Turbo IC 24C04 for a read or write opera-
tion. A1 and A2 are the device address select bits which have
to match the A1 and A2 pin inputs on the 24C04 device. The
B[8] bit is the most significant bit of the memory address.
The (R/W) bit is a high (1) for read and low (0) for write.
DATA INPUT DURING WRITE OPERATION:
During the write operation, the Turbo IC 24C04 latches the
SDA bus signal on the rising edge of the SCL clock.
DATA OUTPUT DURING READ OPERATION:
During the read operation, the Turbo IC 24C04 serially shifts
the data onto the SDA bus on the falling edge of the SCL
clock.
MEMORY ADDRESSING:
The memory address is sent by the master in the form of 2
bytes. Device address A2 and memory address bits B[8],
are included in the device address byte. The remaining
memory address bits B[7:0] are included in the second byte.
The memory address byte can only be sent as part of a write
operation.
BYTE WRITE OPERATION:
The master initiates the byte write operation by issuing a
start condition, followed by the device address byte 1010
(A2) (A1) (B8) 0, followed by the memory address byte, fol-
lowed by one data byte, followed by an acknowledge, then a
stop condition. After each byte transfer, the Turbo IC 24C04
acknowledges the successful data transmission by pulling
the SDA bus low. The stop condition starts the internal
EEPROM write cycle, and all inputs are disabled until the
completion of the write cycle.
4
PAGE WRITE OPERATION:
The master initiates the page write operation by issuing a
start condition, followed by the device address byte 1010
(A2) (A1) (B8) 0, followed by the memory address byte, fol-
lowed by up to 16 data bytes, followed by an acknowledge,
then a stop condition. After each byte transfer, the Turbo IC
24C04 acknowledges the successful data transmission by
pulling SDA low. After each data byte transfer, the memory
address counter is automatically incremented by one. The
stop condition starts the internal EEPROM write cycle only if
the stop condition occurs in the clock cycle immediately fol-
lowing the acknowledge (10th clock cycle). All inputs are dis-
abled until the completion of the write cycle.
POLLING ACKNOWLEDGE:
During the internal write cycle of a write operation in the Turbo
IC 24C04, the completion of the write cycle can be detected
by polling acknowledge. The master starts acknowledge poll-
ing by issuing a start condition, then followed by the device
address byte 1010 (A2) (A1) (B8) 0. If the internal write cycle
is finished, the Turbo IC 24C04 acknowledges by pulling the
SDA bus low. If the internal write cycle is still ongoing, the
Turbo IC 24C04 does not acknowledge because it's inputs
are disabled. Therefore, the device will not respond to any
command. By using polling acknowledge, the system delay
for write operations can be reduced. Otherwise, the system
needs to wait for the maximum internal write cycle time, tWC,
given in the spec.
POWER ON RESET:
The Turbo IC 24C04 has a Power On Reset circuit (POR) to
prevent data corruption and accidental write operations dur-
ing power up. On power up, the internal reset signal is on
and the Turbo IC 24C04 will not respond to any command
until the VCC voltage has reached the POR threshold value.
24C04
PRODUCT INTRODUCTION
Turbo IC, Inc.
Device Address
Byte Write
SDA LINE
DEVICE
ADDRESS
WORD ADDRESS
DATA
S
T
O
P
A
C
K
A
C
K
M
S
B
L
S
B
R
/
W
A
C
K
S
T
A
R
T
W
R
I
T
E
Page Write
SDA LINE
DEVICE
ADDRESS
WORD ADDRESS
DATA (n)
S
T
O
P
A
C
K
A
C
K
M
S
B
L
S
B
R
/
W
A
C
K
S
T
A
R
T
W
R
I
T
E
A
C
K
//
//
DATA (n + x)
5
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