HTML datasheet архив (поиск документации на электронные компоненты) Поиск даташита (1.687.043 компонентов)
Где искать

Datasheet: TE520S40-40LI (Triscend Corp.)

Triscend E5 Customizable Microcontroller

 

Скачать: PDF   ZIP
 

Document Outline

Triscend E5 Customizable
Microcontroller Platform
March 2003 (Version 1.07)
Product Description
1998-2003 by Triscend Corporation. All rights reserved.
Patents pending.
TCH300-0001-001
Subject to change. Visit
www.triscend.com
for the latest revision of this document.
Comments, questions, or suggestions on this document? Please send them to
mailto:info@triscend.com
.
Industry's first complete Customizable
Microcontroller platform
- High-performance, industry-standard
8051/52-compatible microcontroller (10 MIPS
at 40 MHz)
- Up to 64Kbytes of on-chip, dedicated system
RAM (XDATA RAM)
- Up to 2,048 Configurable System Logic (CSL)
cells (roughly 40,000 gates)
- High-performance dedicated internal bus
- Advanced system debug capability
- Stand-alone operation from a single external
memory (code + configuration)
- Advanced four-layer metal, 0.35
CMOS pro-
cess technology, 3.3 volt with 5 volt-tolerant
I/O
Enhanced, high-performance, 8051-based
microcontroller
- Binary- and instruction-set compatible with
other 8051-and 8052-based devices
- 4 cycles per instruction byte provides up to 10
MIPS performance at 40 MHz
- Configurable, extendable architecture sup-
ports user-designed or library-provided pe-
ripherals
- Two-channel DMA controller supporting sin-
gle-clock transfers
- Programmable wait-state capability
- Dual 16-bit data pointers
- Three programmable 16-bit timer/counters
- Programmable, full duplex asynchronous se-
rial communications port
- 256-byte scratchpad RAM
- Protected programmable watchdog timer
- Programmable power-down modes, including
individual PIO options
- Separate 64K address spaces for code and
data
- 12 interrupt sources with three priority levels
- Embedded debugging capabilities

Configurable
System Logic
(CSL)
matrix
PIO
PIO
PIO
PIO
PIO
Bus
Arbiter
Power
Control
Address Bus
Selector
Selector
Data Bus
Clock and
Crystal
Oscillator
Control
Power-On
Reset
To external memory
for initialization and
code storage
Configurable System
Interconnect (CSI) bus
Configurable System
Interconnect bus
socket
CPU
USART
Watchdog
Timer
Interrupt
Unit
256x8
RAM
Timer 0
Timer 1
Timer 2
Accelerated 8051
Selector
Selector
Selector
Address
Mappers
Two-channel
DMA Controller
JTAG Interface
Byte-wide
System RAM
Hardware
Breakpoint Unit
Memory
Interface Unit
Selector
PIO
PIO
PIO
Figure 1. Triscend E5 Customizable MicrocontrollerCustomizable Microcontroller block diagram.
Triscend E5 Customizable Microcontroller Platform
TCH300-0001-001
2
Embedded Configurable System Logic
(CSL) matrix
- Fast, flexible CSL logic cells support combina-
torial logic, arithmetic, memory, sequential,
and bus functions
- Up to 2,048 CSL cells per device
- Easy, synchronous access to and from the
system bus
- Programmable intercommunications network
between system bus, CSL cells, and pro-
grammable I/O (PIO) pins
- Contention-free bi-directional bussing
High-performance, dedicated Configurable
System Interconnect (CSI) system bus
- 8-bit read and write data, 32-bit address
- Up to 40 Mbytes/sec transfer rates
- Simple, synchronous interface to CSL periph-
erals, seamless connection to the microcon-
troller
- Multi-master bus with round-robin arbitration
- Expandable to off-chip function through mem-
ory interface unit (MIU)
- Flexible on-chip address decoders provide
easy access to CSL functions
- Programmable wait-state support
- Open standard
- Forward compatible with future Triscend cus-
tomizable microcontroller devices
Enhanced programmable input/output (PIO)
ports
- Up to 315 user-programmable I/O per device
- Inputs, outputs, or bi-directional ports for the
microcontroller, dedicated peripherals, or pro-
grammable logic peripherals
- Selectable output drive from 4 mA to 12 mA
- BusMinderTM circuit provides pull-up, pull-
down, or weak-follower capability
- Optional input hysteresis
- Optional power-down operation, individually
selectable on every pin
- Input, output and output enable flip-flops for
optimal set-up and clock-to-output perform-
ance
- 5 volt tolerant inputs while operating at 3.3
volts
Memory interface unit (MIU) for flexible,
glue-less interface to external memory
- Direct connect interface to an external
256Kx8 memory for initialization and code
storage
- Expandable from 18 up to 32 address lines
- Variable-speed read/write timing simplifies in-
terface design
- Access external peripherals by sharing MIU
data and address pins
Two-channel advanced DMA controller
- Proxy bus masters for CSL "soft modules"
- Up to 40 Mbytes/s transfer rate (1 byte/cycle)
- Auto-initialization of channels
- Multiple addressing modes
- Software-initiated DMA requests
- Optional interrupt at end of a transfer
- Block data transfers
- CRC checking
- DMA channel request and acknowledge sig-
nals distributed to the CSL matrix
Programmable power-down modes
- Selectively disable function during power-
down
- Typically consumes less than 50 A in full
power-down mode
On-chip oscillator, crystal oscillator ampli-
fier, and clock distribution circuitry
Four-pin IEEE 1149.1 JTAG interface port for
download and debugging
- Supports SAMPLE/PRELOAD, EXTEST, IN-
TEST, BYPASS, and IDCODE instructions
Table 1. Triscend E5 Customizable Microcontroller Family
Device
Embedded
Processor
Core
Dedicated
Resources
System
RAM
Configurable
System
Logic (CSL)
Cells
CSI Bus
Address
Decoders
PIO*
Pins
(Max)
TE502 8Kx8
256
16
92
TE505 16Kx8
512
32
124
TE512 32Kx8
1,152
72
188
TE520
Accelerated
8051
(3) 16-bit counters
USART
Watchdog timer
Interrupt controller
High-speed internal bus
Memory interface unit
2-channel DMA controller
Power management
Power-on reset
Hardware breakpoint unit
JTAG port
40Kx8
2,048
128
252
* Maximum PIO on each base device, actual PIO count depends on package style and initialization mode. See
Table 45
.
3
TCH300-0001-001
- 8051 reset and Customizable Microcontroller
reset
- Full access to the CSI system bus and all ad-
dressable locations
Multiple in-system programming modes
- Unlimited, in-system programmability
- Byte-wide using standard FLASH, EPROM, or
SRAM memories
- Serially using serial sequential-access PROM
memories (SPROMs)
- Via JTAG using internal system RAM to store
program code
- 'Stealth'-mode operation from internal RAM
during battery-backed operation
Dedicated in-system debugging, hardware
breakpoint unit
- Two breakpoint units monitor system address,
data, control, and processor instruction type
-
Breakpoint indicator and control from Config-
urable System Logic (CSL)
Overview
The Triscend E5 Customizable Microcontroller in-
tegrates, on a single device, a performance-
enhanced Accelerated 8051 embedded microcon-
troller, a large block of SRAM, a high-speed dedi-
cated system bus, and configurable logic, inti-
mately connected to the processor and system
bus. The E5 family is a highly integrated, fully
static single-chip system optimized for embedded
systems applications. Each member of the E5
family contains an identical microcontroller and set
of dedicated resources, as shown in
Figure 1
.
However, the size of the dedicated system RAM,
the number of programmable I/O (PIO) pins, and
the amount of configurable system logic grows with
the larger members of the family, as shown in
Table 1
.
The embedded high-performance 8051-based
"Turbo" microcontroller is instruction-compatible
with other industry-standard 8051/52-based de-
vices, leveraging the vast software library for the
8051 architecture. While the instruction cycle for
the original 8051 microcontroller is 12 clock cycles,
the Accelerated 8051 microcontroller provides bet-
ter performance because each instruction cycle is
only four clock cycles. The result is improved per-
formance at the same clock frequency.
The Accelerated 8051 core offers other advan-
tages over the original 8051. The Accelerated
8051 MCU provides a protected watchdog timer
plus an additional data pointer, easing data trans-
fer routines.
The embedded SRAM-based Configurable System
Logic (CSL) matrix provides "derivative on de-
mand" system customization. The high-
performance configurable logic architecture con-
sists of a highly interconnected matrix of CSL cells.
Resources within the matrix provide easy, seam-
less access to and from the internal system bus.
Each CSL cell performs various potential functions,
including combinatorial and sequential logic. The
Configurable System Interconnect (CSI) Bus
CSI Bus Sockets
Configurable System-on-Chip
System Resources
SPI
Serial
Interface
Pulse-Width
Modulator
8-bit UART
with parity
generation/
detection
"Soft" modules
implemented in the
Configurable System Logic
(CSL) matrix
Figure 2. "Soft" modules are built from Configurable System Logic (CSL) resources. Modules
connect to the Customizable Microcontroller system via a Configurable System Inter-
connect (CSI) bus socket, providing easy "drag-and-drop" customization.
Triscend E5 Customizable Microcontroller Platform
TCH300-0001-001
4
combinatorial portion performs Boolean logic op-
erations, arithmetic functions, and memory. The
sequential element performs independently or in
tandem with the combinatorial function.

The abundant programmable input/output blocks
(PIOs) provide the interface between external func-
tions and the internal system bus or configurable
system logic. Each PIO offers advanced I/O op-
tions including selectable output drive current, op-
tional input hysteresis, and programmable low-
power functionality during power-down mode.
A high-performance internal system bus--called
the Configurable System Interconnect (CSI) bus--
interconnects the microcontroller, its peripherals,
and the CSL matrix. The bus provides eight bits of
read data, eight bits of write data, and a 32-bit ad-
dress. Address mapping logic translates the
8051's 16-bit address to the 32-bit address used
by the internal system bus.
Multiple masters arbitrate for bus access. Poten-
tial bus masters include the Accelerated 8051 mi-
crocontroller, the JTAG interface, the read and
write channels of each DMA channel, and the
memory interface unit (MIU) in some modes of op-
eration. Functions implemented in the CSL matrix
can use a DMA channel as a "proxy" master, re-
using the control logic already contained in the
DMA channels to become a master on the CSI
bus.
A memory interface unit (MIU) connects the Tris-
cend E5 Customizable Microcontroller to external
memory. The MIU typically connects to an exter-
nal FLASH-memory device that holds the E5's ini-
tialization program plus the user's code. The MIU
interface is reusable for connections to other ex-
ternal components. The external read, write con-
trol, and chip-select signals are programmable
providing flexible set-up, strobe, and hold timing.
The two-channel DMA controller provides high-
bandwidth communication between functions, up
to 40 Mbytes per second. Its easy-to-use hand-
shake simplifies interface and control logic. Func-
tions from within the CSL matrix can request DMA
transfers, the DMA controller providing "proxy" bus
mastering capabilities.
A large block of fast, byte-wide SRAM provides
internal storage for temporary data storage or for
code. Though typically used for data, code can be
executed from internal RAM, offering faster access
plus security in battery-backed applications.
The majority of the system, including the microcon-
troller, operates from a single bus-clock signal.
Optional sources for the bus clock include driving it
directly from an off-chip signal, connecting an ex-
ternal crystal or ceramic oscillator between the
dedicated crystal-oscillator amplifier pins, or using
the internal ring oscillator. Six other global buffers
provide high-fanout signals to CSL functions. The
Triscend
Configurable
System-on-Chip
(CSoC)
TCK
TMS
TDI
TDO
CE-
OE- D[7:0] A[17:0]
WE-
18
8
PIO
RST-
XTALIN
XTAL
PIO
PIO
PIO
PIO
PIO
VSYS
+3.3V
PIO
PIO
PIO
PIO
PIO
PIO
Up to 125 PIO pins in 208-pin PQFP package
+3.3V
16
VCC
GND
28
GND
JTAG Connector
TCK
TMS
TDI
TDO
Flash ROM
256Kx8
CE- WE- OE- D[7:0] A[17:0]
SLAVE-
+3.3V
VCC
GND
GND
+3.3V
GND
Figure 3. A complete Triscend E520 Customizable Microcontroller design.
5
TCH300-0001-001
bus clock and the global buffers can optionally be
stopped upon a breakpoint event and shut off dur-
ing power-down mode.
Power management control provides selectable
power-down options over internal functions. Fur-
thermore, each PIO provides pin-by-pin power-
down settings.
The E5 Customizable Microcontroller, like other
advanced processors, is built from leading-edge
static CMOS technology. The E5 device is infi-
nitely in-system programmable. A power-on reset
circuit guarantees proper start-up operation after
power is asserted. There are various initialization
(bootstrapping) modes to support different applica-
tion requirements. The E5 can load itself auto-
matically after power-on from an external, byte-
wide boot memory. Optionally, the E5's configura-
tion data is stored in a serial sequential-access
PROM. In serial mode, the user's code is copied
to and executed from the internal SRAM. Serial
mode frees a number of device pins so that they
can be used as user-defined PIO pins.
In security-conscious applications, the user's pro-
gram is stored in internal RAM and battery-backed
using external circuitry. If the E5 Customizable
Microcontroller is in `stealth' mode, it boots from
internal RAM when VCC is re-applied after battery
back up. Stealth mode optionally disables the
JTAG interface port and disables external fetches
via the MIU.
An internal initialization boot ROM controls the
start of initialization during power-on after the RST-
pin is released. The primary purpose of the
initialization boot ROM is to find the user's
initialization data and code stored in the secondary
boot code, usually held in PROM.
Initialization programs can also be downloaded
directly to internal SRAM through the JTAG port.
Likewise, initialization programs can be written to
external flash via JTAG through the MIU interface.
Besides downloading initialization programs, the
JTAG port offers nearly full access to the micro-
controller, peripherals, and CSL functions to aid in
debugging. The JTAG interface can become a bus
master on the internal CSI bus. During system
debugging, the JTAG port also sets up the internal
hardware breakpoint unit.
The hardware breakpoint unit contains two func-
tions that monitor the 8-bit read or write data bus,
the 32-bit internal address bus, control signals and
the type of processor instruction (code or data ac-
cess). Upon a predefined set of conditions, the
breakpoint unit halts execution of the application
program. Via JTAG control, the user can single-
step instruction execution of the processor.
Together, the Accelerated 8051 microcontroller, its
dedicated peripherals, the on-chip RAM, the inter-
nal CSI system bus, and the CSL matrix and PIOs
form a powerful, integrated configurable system.

Accelerated 8051 Microcontroller
The Triscend E5 8051-based Customizable Micro-
controller is fully instruction set compatible with
other industry-standard 8051/8052 microcontrol-
lers. It includes the resources of the standard 8051
including three 16-bit timer/counters; a full-duplex
serial port and twelve interrupt sources with three
priority levels.
The E5 features a performance-enhanced 8-bit
CPU with a redesigned core processor, reducing
unnecessary clock and memory cycles. The in-
struction cycle of a standard 8051 is twelve clock
cycles while the Triscend E5 reduces this to four
clock cycles for the majority of instructions, thereby
improving performance by an average of 1.5 to 3
times.
This naturally speeds up the execution of the in-
structions. Consequently, the E5 offers more
processing power compared to the original 8051,
even using the same frequency crystal. For a
given throughput, the E5 can be operated from a
lower-frequency clock than the original 8051, re-
ducing power consumption.
The E5 also provides dual Data Pointers (DPTRs)
to boost block data memory transfers.
P
P
r
r
o
o
g
g
r
r
a
a
m
m
m
m
a
a
b
b
l
l
e
e
I
I
/
/
O
O
P
P
o
o
r
r
t
t
s
s
The original 8051 offers up to four 8-bit ports, a
total up to 32 lines. In the E5, the 8051 processor
core is embedded with other functions. The proc-
essor optionally connects to as many PIO pins as
required by the application.
U
U
A
A
R
R
T
T
The Triscend E5's UART is a superset of the
UART in the original 8051 family, though offers
timing compatibility. The UART provides en-
hanced features such as automatic address rec-
ognition and frame error detection.
T
T
i
i
m
m
e
e
r
r
s
s
The E5's 8051-based microcontroller has three 16-
bit timers that are functionally similar to the timers
of the original 8051 family. When used as timers,
they optionally operate at either 4 clocks or 12
clocks per count, thus providing a mode that emu-
lates the timing of the original 8051.
© 2017 • ChipFind
Контакты
Главная страница