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Datasheet: 16C552 (Texas Instruments)

Dual Asychronous Communications Element With Fifo

 

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Texas Instruments
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B DECEMBER 1990 REVISED MARCH 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
IBM PC/AT
TM
Compatible
D
Two TL16C550 ACEs
D
Enhanced Bidirectional Printer Port
D
16-Byte FIFOs Reduce CPU Interrupts
D
Independent Control of Transmit, Receive,
Line Status, and Data Set Interrupts on
Each Channel
D
Individual Modem Control Signals for Each
Channel
D
Programmable Serial Interface
Characteristics for Each Channel:
5-, 6-, 7-, or 8-bit Characters
Even-, Odd-, or No-Parity Bit Generation
and Detection
1-, 1 1/2-, or 2-Stop Bit Generation
D
3-State TTL Drive for the Data and Control
Bus on Each Channel
D
Hardware and Software Compatible With
TL16C452
description
28 29
INT1
INT2
SLIN
INIT
AFD
STB
GND
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
INT0
BDO
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
SOUT1
DTR1
RTS1
CTS1
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
TXRDY0
V
DD
RTS0
DTR0
SOUT0
31 32 33 34
FN PACKAGE
(TOP VIEW)
ACK
PE
8 7
6
5
4
9
3
GND
RI1
DSR1
CLK
CS1
TRI
PEMD
IOW
IOR
CS2
RESET
DCD0
RI0
DSR0
CS0
A2
A1
A0
1 68 67
2
35 36 37 38 39
66 65
27
GND
CTS0
BUSY
SLCT
64 63 62 61
40 41 42 43
SIN0
TXRDY1
ENIRQ
ERR
SIN1
RXRDY1
RXRDY0
DCD1
V
DD
V
DD
description
The TL16C552 is an enhanced dual channel version of the popular TL16C550 asynchronous communications
element (ACE). The device serves two serial input/output interfaces simultaneously in microcomputer or
microprocessor-based systems. Each channel performs serial-to-parallel conversion on data characters
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1996, Texas Instruments Incorporated
IBM PC/AT is a trademark of International Business Machines Corporation.
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B DECEMBER 1990 REVISED MARCH 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted
by the CPU. The complete status of each channel of the dual ACE can be read at any time during functional
operation by the CPU. The information obtained includes the type and condition of the transfer operations being
performed and the error conditions.
In addition to its dual communications interface capabilities, the TL16C552 provides the user with a fully
bidirectional parallel data port that fully supports the parallel Centronics-type printer. The parallel port and the
two serial ports provide IBM PC/AT-compatible computers with a single device to serve the three system ports.
A programmable baud rate generator is included that can divide the timing reference clock input by a divisor
between 1 and (2
16
1).
The TL16C552 is housed in a 68-pin plastic leaded chip carrier.
functional block diagram
CTS0
DSR0
DCD0
RI0
SIN0
CS0
DB DB7
RTS0
DTR0
SOUT0
INT0
RXRDY0
TXRDY0
RTS1
DTR1
SOUT1
INT1
RXRDY1
TXRDY1
BDO
24
25
26
45
9
22
12
11
10
60
61
42
53 46
57
56
55
58
59
CTS1
DSR1
DCD1
RI1
SIN1
CS1
28
31
29
30
41
32
14 21
8
8
13
5
8
6
62
3
36
37
39
4
A0 A2
IOW
IOR
RESET
CLK
ERR
SLCT
BUSY
PE
ACK
PEMD
CS2
ENIRQ
63
65
66
67
68
1
38
43
8
8
PD0 PD7
INIT
AFD
STB
SLIN
INT2
44
Select
and
Control
Logic
Parallel
Port
ACE
#2
ACE
#1
35 33
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B DECEMBER 1990 REVISED MARCH 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
ACK
68
I
Line printer acknowledge. ACK goes low to indicate a successful data transfer has taken place.
It generates a printer port interrupt during its positive transition.
AFD
56
I/O
Line printer autofeed. AFD is an open-drain line that provides the printer with an active-low signal
when continuous form paper is to be autofed to the printer. This terminal has an internal pullup
resistor to VDD of approximately 10 k
.
A0, A1, A2
35, 34, 33
I
Address lines A0 A2. A0, A1, and A2 select the internal registers during CPU bus operations. See
Table 2 for the decode of the serial channels and Table 13 for the decode of the parallel printer port.
BDO
44
O
Bus buffer output. BDO is an active-high output that is asserted when either serial channel or the
parallel port is read. This output can control the system bus driver (74LS245).
BUSY
66
I
Line printer busy. BUSY is an input line from the printer that goes high when the printer is not ready
to accept data.
CLK
4
I
Clock input. CLK is an external clock input to the baud rate divisor of each ACE.
CS0, CS1, CS2
32, 3, 38
I
Chip selects. CS0, CS1, and CS2 act as an enable for the write and read signals for the serial
channels 1 (CS0) and 2 (CS1). CS2 enables the signals to the printer port.
CTS0, CTS1
28, 13
I
Clear to send inputs. The logical state of CTS0 or CTS1 is reflected in the CTS bit of the modem
status register (CTS is bit 4 of the modem status register, written MSR4) of each ACE. A change
of state in either CTS terminal, since the previous reading of the associated modem status register,
causes the setting of delta clear to send (
CTS) bit (MSR0) of each modem status register.
DB0 DB7
14 21
I/O
Data bits DB0 DB7. The data bus provides eight 3-state I/O lines for the transfer of data, control,
and status information between the TL16C552 and the CPU. These lines are normally in a
high-impedance state except during read operations. D0 is the least significant bit (LSB) and is the
first serial data bit to be received or transmitted.
DCD0, DCD1
29, 8
I
Data carrier detect. DCD is a modem input. Its condition can be tested by the CPU by reading the
MSR7 (DCD) bit of the modem status registers. The MSR3 (delta data carrier detect or
DCD) bit
of the modem status register indicates whether the DCD input has changed states since the
previous reading of the modem status register. DCD has no affect on the receiver.
DSR0, DSR1
31, 5
I
Data set ready inputs. The logical state of DSR0 and DSR1 is reflected in MSR5 of its associated
modem status register. The MSR1 (delta data set ready or
DSR) bit indicates whether the
associated DSR terminal has changed states since the previous reading of the modem status
register.
DTR0, DTR1
25, 11
O
Data terminal ready lines. DTR0 and DTR1 can be asserted low by setting modem control register
bit 0 (MCR0) of its associated ACE. This signal is asserted high by clearing the DTR bit (MCR0)
or whenever a reset occurs. When active (low), the DTR terminal indicates that its ACE is ready
to receive data.
ENIRQ
43
I
Parallel port interrupt source mode selection. When ENIRQ is low, the PC/AT mode of interrupts
is enabled. In this mode, the INT2 output is internally connected to the ACK input. When the ENIRQ
input is tied high, the INT2 output is internally tied to the PRINT signal in the line printer status
register. INT2 is latched high on rising edge of ACK.
ERR
63
I
Line printer error. ERR is an input line from the printer. The printer reports an error by holding this
line low during the error condition.
GND
7, 27, 54
Ground (0 V). All terminals must be tied to ground for proper operation.
INIT
57
I/O
Line printer initialize. INIT is an open-drain line that provides the printer with an active-low signal,
which allows the printer initialization routine to be started. This terminal has an internal pullup
resistor to VDD of approximately 10 k
.
IOR
37
I
Input/output read strobe. IOR is an active-low input that enables the selected channel to output
data to the data bus (DB0 DB7). The data output depends upon the register selected by the
address inputs A0, A1, A2, and chip select. Chip select 0 (CS0) selects ACE #1, chip select 1 (CS1)
selects ACE #2, and chip select 2 (CS2) selects the printer port.
IOW
36
I
Input/output write strobe. IOW is an active-low input causing data from the data bus to be input to
either ACE or to the parallel port. The destination depends upon the register selected by the address
inputs A0, A1, A2, and chip selects CS0, CS1, and CS2.
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B DECEMBER 1990 REVISED MARCH 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
INT0, INT1
45, 60
O
Serial channel interrupts. INT0 and INT1 are 3-state serial channel interrupt outputs (enabled by bit
3 of the MCR) that go active (high) when one of the following interrupts has an active (high) condition
and is enabled by the interrupt enable register of its associated channel: receiver error flag, received
data available, transmitter holding register empty, and modem status. The interrupt is cleared upon
appropriate service. When reset, the interrupt output is in the high-impedance state.
INT2
59
O
Printer port interrupt. INT2 is an active-high, 3-state output generated by the positive transition of ACK.
It is enabled by bit 4 of the write control register. Upon a reset, the interrupt output is in the
high-impedance state. Its mode is also controlled by ENIRQ.
PD0 PD7
53 46
I/O
Parallel data bits (0 7). These eight lines (PD0 PD7) provide a byte wide input or output port to the
system.
PE
67
I
Printer paper empty. PE is an input line from the printer that goes high when the printer runs out of
paper.
PEMD
1
I
Printer enhancement mode. When low, PEMD enables the write data register to the PD0 PD7 lines.
A high on this signal allows direction control of the PD0 PD7 port by the DIR bit in the control register.
PEMD is usually tied low for the printer operation.
RESET
39
I
Reset. When low, RESET forces the TL16C552 into an idle mode in which all serial data activities are
suspended. The modem control register along with its associated outputs are cleared. The line status
register is cleared except for the THRE and TEMT bits, which are set. All functions of the device remain
in an idle state until programmed to resume serial data activities. This input has a hysteresis level of
typically 400 mV.
RTS0, RTS1
24, 12
O
Request to send outputs. RTSx is asserted low by setting MCR1, bit 1 of its UARTs modem control
register. Both RTSx terminals are set by RESET. A low on the RTSx terminal indicates that its ACE has
data ready to transmit. In half-duplex operations, RTSx controls the direction of the line.
RXRDY0,
RXRDY1
9, 61
O
Receiver ready. RXRDY0 and RXRDY1 are receiver direct memory access (DMA) signaling
terminals. One of two types of DMA signaling can be selected using FIFO control register bit 3 (FCR3)
when operating in the FIFO mode. Only DMA mode 0 is allowed when operating in the TL16C450
mode. For signal transfer DMA (a transfer is made between CPU bus cycles), mode 0 is used. Multiple
transfers that are made continuously until the receiver FIFO has been emptied are supported by
mode 1.
Mode 0. RXRDYx is active (low) when in the FIFO mode (FCR0=1, FCR3=0) or when in the TL16C450
mode (FCR0=0) and the receiver FIFO or receiver holding register contain at least one character.
When there are no more characters in the receiver FIFO or receiver holding register, the RXRDYx
terminal goes inactive (high).
Mode 1. RXRDYx goes active (low) in the FIFO mode (FCR0=1) when FCR3=1 and the time-out or
trigger levels have been reached. It goes inactive (high) when the FIFO or receiver holding register is
empty.
RI0, RI1
30, 6
I
Ring indicator inputs. RI0 and RI1 are modem control inputs. Their condition is tested by reading
MSR6 (RI) of each ACE. The modem status register outputs trailing edge of ring indicator (TERI or
MSR2) that indicates whether either input has changed states from high to low since the previous
reading of the modem status register.
SIN0, SIN1
41, 62
I
Serial data inputs. SIN0 and SIN1 are serial data inputs that move information from the communication
line or modem to the TL16C552 receiver circuits. Mark (set) is a high state and a space (cleared) is
low state. Data on the serial data inputs is disabled when operating in the loop mode.
SLCT
65
I
Printer selected. SLCT is an input line from the printer that goes high when the printer has been
selected.
SLIN
58
I/O
Line printer select. SLIN is an open-drain input that selects the printer when it is active (low). This
terminal has an internal pullup resistor to VDD of approximately 10 k
.
SOUT0, SOUT1
26, 10
O
Serial data outputs. SOUT0 and SOUT1 are the serial data outputs from the ACE transmitter circuitry.
A mark is a high state and a space is a low state. Each SOUT is held in the mark condition when the
transmitter is disabled, when RESET is true (low), when the transmitter register is empty, or when in
the loop mode.
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B DECEMBER 1990 REVISED MARCH 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
STB
55
I/O
Printer strobe. STB is an open-drain line that provides communication between the TL16C552 and the
printer. When it is active (low), it provides the printer with a signal to latch the data currently on the
parallel port. This terminal has an internal pullup resistor to VDD of approximately 10 k
.
TRI
2
I
3-state control. TRI controls the 3-state control of all I/O and output terminals. When TRI is asserted,
all I/O and outputs become high impedance, allowing board level testers to drive the outputs without
overdriving the internal buffers. This terminal is level sensitive, is a CMOS input, and is pulled down
with an internal resistor that is approximately 5 k
.
TXRDY0,
TXRDY1
22, 42
O
Transmitter ready. TXRDY0 and TXRDY1 are transmitter ready signals. Two types of DMA signaling
are available. Either can be selected using FCR3 when operating in the FIFO mode. Only DMA mode
0 is allowed when operating in the TL16C450 mode. Single-transfer DMA (a transfer is made between
CPU bus cycles) is supported by mode 0. Multiple transfers that are made continuously until the
transmitter FIFO has been filled are supported by mode 1.
Mode 0. When in the FIFO mode (FCR0=1, FCR3=0) or in the TL16C450 mode (FCR0=0) and there
are no characters in the transmitter holding register or transmitter FIFO, TXRDY are active (low). Once
TXRDY is activated (low), it goes inactive after the first character is loaded into the holding register of
transmitter FIFO.
Mode 1. TXRDYx goes active (low) if in the FIFO mode (FCR0=1) when FCR3=1 and there are no
characters in the transmitter FIFO. When the transmitter FIFO is completely full, TXRDYx goes inactive
(high).
VDD
23, 40, 64
Power supply. VDD is the power supply requirement is 5 V
5%.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
DD
(see Note 1)
0.5 V to V
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
0.5 V to V
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation
500 mW
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
10
C to 70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage levels are with respect to ground (VSS).
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VDD
4.75
5
5.25
V
Clock high-level input voltage, VIH(CLK)
2
VDD
V
Clock low-level input voltage, VIL(CLK)
0.5
0.8
V
High-level input voltage, VIH
2
VDD
V
Low-level input voltage, VIL
0.5
0.8
V
Clock frequency, fclock
8
MHz
Operating free-air temperature range, TA
0
70
C
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