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Datasheet: bl1208h (Samsung semiconductor)

BL1208H 10Bit 5MSPS ADC BL1208H ; Function = ADC ; Configuration = 10BIT 5MSPS ; Library Type = STD85 ; Characteristic = 5V/20mA

 

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Samsung semiconductor
BL1208H
10BIT 5MSPS ADC
SEC ASIC
ANALOG
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The BL1208H is a CMOS 10-bit A/D converter for
video applications. It is a three-step pipelined A/D
converter which consists of sample & hold, three
multiplying DACs, a 4-bit flash adc and three 3-bit
flash adcs.
The maximum conversion rate of BL1208H is 5MSPS
and supply voltage is 5V single.
TYPICAL APPLICATIONS
- PC or computer based video signal processing such
as multi-media, scanner, etc.
- General Purpose video applications including
camcorder, digital video, broad-casting and studio
equipments.
- Medical electronics such as digital scope, transit
recorder, radar.
FEATURES
- Resolution : 10Bit
- Differential Linearity Error : 1.0 LSB
- Integral Linearity Error : 1.0 LSB
- Maximum Conversion Rate : 5MSPS
- Sample & Hold Function Implemented
- Low Power Consumption : 100mW
- Power Supply : 5V Single
- Operation Temperature Range : -40C ~85C
10BIT 5MSPS ADC
BL1208H
ITEST
STBY
sah
mdac1
mdac2
mdac3
flash1
flash2
flash3
flash4
dclogic
mbias
ckgen
CKIN
REFMID
refgen
VREF
AGND
AINT
STCB
EOC
DO[9:0]
OVF
UDF
Ver 1.1 (Feb. 2000)
No responsibility is assumed by SEC for its use nor for any
infringements of patents or other rights of third parties that may
result from its use. The content of this datasheet is subject to
change without any notice
BL1208H
10BIT 5MSPS ADC
SEC ASIC
ANALOG
CORE PIN DESCRIPTION
NAME
I/O TYPE
I/O PAD
PIN DESCRIPTION
AINT
AI
piar50_bb
Analog Input
(Input Range : 0V ~ 3.2V)
REFMID
AO
piar50_bb
Reference Mid Point (Test Pin)
VREF
AI
pia_bb
Reference Voltage (3.2V)
AGND
AG
vssa
Analog Ground
VDDA
AP
vdda
Analog Power ( 5V )
VSSA
AG
vssa
Analog Ground
ITEST
BD
pia_bb
open=use internal bias point
STBY
DI
picc_bb
high=power saving standby mode
(normally = gnd)
CKIN
DI
picc_bb
Sampling Clock Input
DO[9:0]
DO
pot2_bb
Digital Output
OVF
DO
pot2_bb
Overflow
UDF
DO
pot2_bb
Underflow
STCB
DI
picc_bb
Start of Conversion(normally high)
EOC
DO
pot2_bb
End of Conversion
VBB
AB
vbba
Sub Bias
VSSD
DG
DG
Digital Ground
VDDD
DP
DP
Digital Power
CORE CONFIGURATION
I/O TYPE ABBR.
- AI : Analog Input
- DI : Digital Input
- AO : Analog Output
- DO : Analog Output
- AP : Analog Power
- AG : Analog Ground
- AB : Analog Sub Bias
- DP : Digital Power
- DG : Digital Ground
- DB : Digital Sub Vias
- BD : Bidirectional Port
bl1208h
AINT
EOC
REFMID
ITEST
VREF
DO[9:0]
OVF
UDF
AGND
CKIN
STBY
STCB
VDDA
VSSA
VSSD
VDDD
VBB
2 / 12
BL1208H
10BIT 5MSPS ADC
SEC ASIC
ANALOG
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Value
Unit
Supply Voltage
VDD
7.0
V
Analog Input Voltage
AIN
VSS to VDD
V
Digital Input Voltage
CLK
VSS to VDD
V
Digital Output Voltage
V
OH
, V
OL
VSS to VDD
V
Reference Voltage
VREF
3.2
V
Storage Temperature Range
Tstg
-45 to 125
C
NOTES
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently.
Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each
condition value is applied with the other values kept within the following operating conditions and function
operation under any of these conditions is not implied.
2. All voltages are measured with respect to VSS unless otherwise specified.
3. 100pF capacitor is discharged through a 1.5K
resistor (Human body model)
RECOMMENDED OPERATING CONDITIONS
Characteristics
Symbol
Min
Typ
Max
Unit
Supply Voltage
VDDA - VSSA
VDDD - VSSD
4.75
5.0
5.25
V
Supply Voltage Difference
VDDA - VDDD
-0.1
0.0
0.1
V
Reference Input Voltage(Internally)
VREF
-
3.2
-
V
Analog Input Voltage
AINT
0
-
3.2
V
Digital Input 'L' Voltage
Digital Input 'H' Voltage
V
IL
V
IH
-
4.5
-
-
0.5
-
V
Operating Temperature
Topr
0
-
70
C
NOTES
1. It is strongly recommended that all the supply pins (VDDA, VDDD) be powered from the same source to avoid
power latch-up.
3 / 12
BL1208H
10BIT 5MSPS ADC
SEC ASIC
ANALOG
DC ELECTRICAL CHARACTERISTICS
Characteristics
Symbol
Min
Typ
Max
Unit
Conditions
Reference Current
IREF
1.5
2
3
mA
Differential Linearity Error
DLE
-
-
1.0
LSB
AINT : 0 ~ 3.2V
(Ramp Input)
Integral Linearity Error
ILE
-
-
1.0
LSB
Fck : 1MHz
20MHz
Bottom Offset Voltage Error
EOB
-
-
20
LSB
Top Offset Voltage Error
EOT
-
-
20
LSB
NOTES
1. Converter Specifications (unless otherwise specified)
VDDA=5.0V
VDDD=5.0V
VSSA=GND
VSSD=GND
Ta=25C
2. TBD : To Be Determined
AC ELECTRICAL CHARACTERISTICS
Characteristics
Symbol
Min
Typ
Max
Unit
Conditions
Maximum Conversion Rate
fc
5
-
-
MSPS
AINT : 1MHz Sine Signal
(source resolution > 12bit)
Dynamic Supply Current
Ivdd
-
20
25
mA
fc=5MHz
(without system load)
Signal - to - Noise, Distortion
Ratio
SNDR
50
54
-
dB
AINT = 200KHz
fc = 5MHz
4 / 12
BL1208H
10BIT 5MSPS ADC
SEC ASIC
ANALOG
TIMING DIAGRAM( Main Function )
track
hold
track
hold
track
hold
track
hold
track
hold
ref sample
amplify
precharge
latch
track latch
encoding
input
sample
residue
amplify
input
sample
residue
amplify
ref sample
latch
track latch
encoding
amplify
precharge
input
sample
residue
amplify
input
sample
residue
amplify
ref sample
latch
track
amplify
precharge
DATA
AINT
CKIN
SHA
MDAC1
FLASH1
FLASH2
MDAC2
FLASH3
DATA
input
sample
residue
amplify
input
sample
residue
amplify
ref sample
latch
track
amplify
precharge
MDAC3
FLASH4
latch
encoding
latch
encoding
5 / 12
BL1208H
10BIT 5MSPS ADC
SEC ASIC
ANALOG
FUNCTIONAL DESCRIPTION
1. BL1208H is a four step A/D Converter
comprising a 4-bit flash ADC, three 3-bit flash
ADC and three multiplying DAC. The N-bit
flash
ADC
is
composed
of
2
(n-1)
latching
comparators, and multiplying DAC is composed
of 2*(N+2) capacitors and two fully-differential
amplifier.
2. BL1208H operates as follows. During the first
"L" cycle of external clock the analog input data
is tracked and sampled, and the input is held
from the rising edge of the external clock, which
is fed to the first 4-bit flash ADC, and the first
multiplying DAC. Multiplying DAC reconstructs
a voltage corresponding to the first 4-bit ADC's
output, and finally amplifies a residue voltage by
2
3
. The second 3-bit flash ADC, and MDAC are
worked as same manner, finally amplifiers a
residue voltage, which is the difference between
first MDAC's output and reconstructed voltage by
2
2
. The third 3-bit flash ADC, and MDAC are
worked as previous stages. Finally amplified
residue voltage at the third multiplying DAC is
fed to the last 3-bit flash ADC decides final
3-bit digital digital code.
3. BL1208H has the error correction scheme, which
handles the output from mismatch in the first,
second, third and fourth flash ADC.
MAIN BLOCK DESCRIPTION
1. SAH
SAH(track and hold) is the circuit that samples
the analog input signal and hold that value until
next sample-time. It is good as small as its
different value between analog input signal and
output signal. SAH amp gain must be higher
than 66dB at least for less than 1/2LSB of SAH
error voltage at 10bit ADC and its conversion
frequency is 5MHz, its settling-time must be
shorten than 18ns. This SAH is consist of fully
differential op amp, switching tr. and sampling
capacitor.
The
sampling
clock
are
non-overlapping
clocks(Q1,Q2)
and
sampling
capacitor value is 1.2pF. SAH uses independent
bias to protect interruption of any other circuit.
SAH amp is designed that open-loop dc gain is
higher than 70dB, phase margin is higher than
60degree. Its input block is designed to be the
rail-to-rail
architecture
using
complementary
different pair.
2. FLASH
The 4-bit flash converter compare analog signal
(SAH output) with reference voltage, and that
result transfer to MDAC and digital correction
logic block. It is realized fully differential
comparators of 15EA. Considering self-offset,
dynamic feed through error, it should distinguish
40mV at least. First, the comparators charge the
reference voltage at the sampling capacitors
before transferred SAH output. Q2 works this
process
and
Q1
discharges
this
sampling
capacitance. That is, the comparators compare
relative different values dual input voltage with
dual reference voltage. Its output during Q1
operation is stored at the pre-latch block by
Q1P.
3. MDAC
MDAC is the most important block at this
ADC and it decides the characteristics. MDAC
is consist of amp1,amp2, selection logic and
capacitor array(c_array). C_array's compositions
are the capacitors to charge the analog input and
and the reference voltage, Switches to control
the path. Selection logic controls the c_array
internal switches. If Q1 is high, selection's
output are all low, the switches of tsw1 are off,
the switches of tsw2 are all on. Therefore the
capacitors of c_array charge analog input values
holded at SAH. If Q2 is high, it is reversed and
final MDAC output voltage is described the
following equation.
Vout = (AIN - Vref)*8-Vref/2
AIN=AINT-2.5V
6 / 12
BL1208H
10BIT 5MSPS ADC
SEC ASIC
ANALOG
TIMING DIAGRAM (OPTIONAL)
STCB
EOC
Pipeline Delay
10nS
3nS
T
SAFE
CKIN
STCB
1. Main Waveform
2. STCB / CKIN
The A/D converter does data conversion when STCB(Start of Conversion Bar) signal is just "HIGH".
Otherwise, output data (DO[9:0]) keeps the current states.
The STCB signal should be changed during "Tsafe" with the "HIGH" level of the clock to operation as shown
in the main waveform.
3. Pipeline Delay
After STCB goes "HIGH", the A/D converter requires the pipeline delay of 3 clock period to generate EOC
signal and data outputs.
A1
A2
A6
DO1
A4
AINT
CKIN
STCB
EOC
DO
DO2
DO4
DO6
7 / 12
BL1208H
10BIT 5MSPS ADC
SEC ASIC
ANALOG
CORE EVALUATION GUIDE
1. ADC function is evaluated by external check on the bidirectional pads connected to input nodes of
HOST DSP back-end circuit.
2. The reference voltages may be biased internally through resistor devider.
NOTES
: 10uF Electronic Capacitor
unless Otherwise Specified
: 0.1uF Ceramic Capacitor
unless Otherwise Specified
bl1208h
AINT
DO[9:0]
EOC
REFMID CML
VREF AGND
ITEST
STBY
CKIN
STCB
Digital Mux
Bidirectional
PAD
HOST
DSP
CORE
DO[9:0]
DO[9:0]
(ADC Function Test &
externally forced Digital Input)
DC : 3.2V
100
OVF UDF
100
100
OVF
UDF
8 / 12
BL1208H
10BIT 5MSPS ADC
SEC ASIC
ANALOG
PACKAGE CONFIGURATION
NOTES
1. You can test ADC function by checking external bidirectional pad connected to internal signal path.
2. ESD (ElectroStatic Discharge) sensitive device. Although the digital control inputs are diode protected, permanent
damage may occur on devices subjected to high electrostatic discharges. It is recommended that unused devices be
stored in conductive foam or shunts to avoid performance degradation or loss of functionality. The protective foam
should be discharged to the destination socket before devices are inserted.
3. NC denotes "No Connection".
BL1208H
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
REFBOT
REFMID
VDDA
VSSA
CML
AINC
MINV
NC
VDDA
VSSA
AINT
LINV
NC
VDDR
VSSR
CKIN
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
D<2>
D<3>
D<4>
D<5>
D<6>
D<7>
STCB
OVF
UDF
NC
NC
NC
D<9>
D<8>
EOC
VBB
NC
REFTOP
REFTS
REFBOT
1
4
3
2
VSSD
VSSD
VDDD
VDDD
45
48
47
46
21
22
23
24
25
26
27
28
NC
ITEST
NC
NC
TRISTATE
NC
D<0>
D<1>
Analog Input
(Input Range:0~3.2V)
Clock Signal
3.2V
Reference
Top
1.6V
Reference
Bottom
5V
PAD Power
5V
Analog Power
GND
GND
5V
Digital
Power
Digital Output Bits 2 Through 9
Digital Output Bits 0 and 1
: 10uF ELECTROLYTIC CAPACITOR
UNLESS OTHERWISE SPECIFIED
: 0.1uF CERAMIC CAPACITOR
UNLESS OTHERWISE SPECIFIED
NOTES
DC 0V
9 / 12
BL1208H
10BIT 5MSPS ADC
SEC ASIC
ANALOG
PACKAGE PIN DESCRIPTION
NAME
PIN NO.
I/O TYPE
PIN DESCRIPTION
REFTOP
2
AI
External Reference Top Bias.(3.2V)
REFBOT
3
AI
External Reference Bottom Bias.(1.6V)
REFTS
4
AI
External Reference Top Sense(3.2V)
REFBS
5
AI
External Reference Bottom Sense(1.6V)
REFMID
6
AO
Reference Mid Point ( Test Pin )
VDDA
7,8
AP
5V Analog Power
VSSA
9,10
AG
Analog Grounf
AINT
11
AI
Analog Input (+)
Input Range : 0~3.2V
CML
12
AO
Internal Bias Point ( Test Pin )
AINC
13
AI
Analog Input. (-)
DC 1.6V
MINV
14
DI
high = invert MSB(normally gnd)
LINV
15
DI
high = invert all LSB(normally gnd)
VDDR
17
PP
Ouput Driver Power
VSSR
18
PG
Output Driver Ground
STBY
19
DI
High = power saving standby mode
(normally gnd)
CKIN
20
DI
Sampling Clock Input
ITEST
22
BD
open=use internal bias point
TRISTATE
25
DI
high = high impedance digital output
(normally gnd)
DO[9:0]
27~36
DO
Digital Output
UDF
40
DO
Underflow Output Signal
OVF
41
DO
Overflow Output Signal
STCB
42
DI
Start of Conversion (normally high)
EOC
43
DO
End of Conversion
VBB
44
DB
Substrate Ground
VSSD
45,46
DG
Digital Ground
VDDD
47,48
DP
Digital Power
NOTES
1. I/O TYPE PP and PG denote PAD Power and PAD Ground respectively.
10 / 12
BL1208H
10BIT 5MSPS ADC
SEC ASIC
ANALOG
USER GUIDE
1. Resolution Control.
- Modular structure is the most important feature of BL1208H.
- You can get any resolution you want by combining each primary module (MDAC + FLASH) without major
circuit change.
- It means you don't have to redesign the most difficult analog block for another resolution.
- But this simple resolution control method has a limit up to 10bits, otherwise the internal op-amp must be
redesigned.
2. Speed Up
- The initial target speed of BL1208H was 5MHz, but it proved to operate well at 10MHz or more due to a
lot of design margin.
3. Input Range Variation.
- The default of the input of this ADC is single 0V ~ +3.2V.
- The bias voltage of AINT is 0V~3.2V..
- In order to alter to another input voltage range, change the voltage values of AINT after setting VREF to the
maximum value of input range.
4. Verilog Modeling
- Verilog modeling needs 64bits for only one analog real signal.
ain
sha
mdac1
mdac2
mdac3
flash1
flash2
flash3
flash4
dclogic
10bit
module
11 / 12
BL1208H
10BIT 5MSPS ADC
SEC ASIC
ANALOG
FEEDBACK REQUEST
It should be quite helpful to our ADC core development if you specify your system requirements on
ADC in the following characteristic cheking table and fill out the additional questions.
We appreciate your interest in our products. Thank you very much.
Characteristic
Min
Typ
Max
Unit
Remarks
Analog Power Supply Voltage
V
Digital Power Supply Voltage
V
Bit Resolution
Bit
Reference Input Voltage
V
Analog Input Voltage
Vpp
Operating Temperature
C
Integral Non-linearity Error
LSB
Differential Non-linearity Error
LSB
Bottom Offset Voltage Error
mV
Top Offset Voltage Error
mV
Maximum Conversion Rate
MSPS
Dynamic Supply Current
mA
Power Dissipation
mW
Signal-to-noise Ratio
dB
Pipeline Delay
CLK
Digital Output Format
(Provide detailed description &
timing diagram)
1. Between single input-output and differential input-output configurations, which one is suitable for your
system and why?
2. Please comment on the internal/external pin configurations you want our ADC to have, if you have
any reason to prefer some type of configuration.
3. Freely list those functions you want to be implemented in our ADC, if you have any.
12 / 12
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