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Datasheet: adc1395x (Samsung semiconductor)

ADC1395X 0.13µm 10-BIT 500KSPS ADC ; Function = ADC ; Configuration = 10BIT 500KSPS ; Library Type = - ; Characteristic = -

 

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Samsung semiconductor
0.13

m 10-BIT 500KSPS ADC
ADC1395X
1
GENERAL DESCRIPTION
The adc1395x is a CMOS 3.3V 10-bit analog-to- digital converter (ADC). It converts the analog input signal into
12-bit binary digital codes at a maximum conversion rate of 500KSPS with 2.5MHz clock.
The device is a recycling type monolithic ADC with an on-chip sample-and-hold function. The ADC has power
down mode.
FEATURES
-- Resolution: 10-bit
-- Maximum conversion rate: 500KSPS
-- Main clock: 2.5MHz
-- Power supply: 3.3V
0.3V
-- Total current: 10uA (Standby Mode)
2mA (Normal Operation)
-- Input range: 0.0V ~ 3.3V (3.3V
P-P
)
-- Differential linearity error:
1.0 LSB (Max)
-- Integral linearity error:
3.0 LSB (Max.)
-- Signal to noise & distortion ratio: 54dB
-- Digital output: CMOS Level
-- Operating temperature range: 40
C ~ 85
C
TYPICAL APPLICATIONS
-- MICOM Interface
-- Portable equipment
-- Low-voltage low-power application
ADC1395X
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m 10-BIT 500KSPS ADC
2
FUNCTIONAL BLOCK DIAGRAM
CLOCK
GEN
AINT
VREF
AGND
DO[9:0]
STC
CKIN
STBY
CML
GEN
REF
GEN
MAIN
BIAS
FLASH2
FLASH1
Digital Logic
EOC
MDAC1
MDAC2
Ver 1.0 (April. 2002)
No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may
result from its use. The content of this data sheet is subject to change without any notice.
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m 10-BIT 500KSPS ADC
ADC1395X
3
CORE PIN DESCRIPTION
Name
I/O Type
I/O Pad
Pin Description
VREF
AI
phia_abb
Reference top (3.3V)
AGND
AI
phia_abb
Reference bottom (0.0V)
AVDD33A1
AP
vdd33th_abb
Analog power (3.3V)
AVBB33A1
AG
vbbh_abb
Analog sub bias (0.0V)
AVSS33A1
AG
vssth_abb
Analog ground (0.0V)
AINT
AI
phiar50_abb
Analog input (input range: 0.0V ~ 3.3V)
STBY
DI
phicc_abb
VDD = Power saving (standby),
GND = Normal
CKIN
DI
phicc_abb
Sampling clock input
D[11:0]
DO
phob4_abb
Digital output
EOC
DO
phob4_abb
End of conversion signal
STC
DI
phicc_bb
Start of conversion signal
AVSS33A2
DG
vssth_abb
Digital GND (0.0V)
AVDD33A2
DP
vdd33th_abb
Digital power (3.3V)
I/O
Type
Abbr.
-- AI: Analog Input
-- DI: Digital Input
-- AO: Analog Output
-- DO: Analog Output
-- AP: Analog Power
-- AG: Analog Ground
-- DP: Digital Power
-- DG: Digital Ground
-- AB: Analog Bi-Direction
-- DB: Digital Bi-Direction
ADC1395X
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m 10-BIT 500KSPS ADC
4
CORE CONFIGURATION
STBY
CKIN
AINT
VREF
AGND
AVDD33A
AVSS33A
AVBB33A
AVDD33D
AVSS33D
[MSB:LSB]
STC
DO[9:0]
EOC
adc1395x
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m 10-BIT 500KSPS ADC
ADC1395X
5
ABSOLUTE MAXIMUM RATINGS
Characteristics
Symbol
Value
Unit
Supply voltage
VDD
4.5
V
Analog input voltage
AINT
VSS to VDD
V
Digital input voltage
CKIN
VSS to VDD
V
Reference voltage
VREF / AGND
VSS to VDD
V
Storage temperature range
Tstg
45 to 150
C
Operating temperature range
Topr
45 to 80
C
NOTES:
1.
Absolute maximum rating specifies the values beyond which the device may be damaged permanently. Exposure to
absolute maximum rating conditions for extended periods may affect reliability. Each condition value is applied
with the other values kept within the following operating conditions and function operation under any of these conditions
is not implied.
2.
All voltages are measured with respect to VSS unless otherwise specified.
3.
100pF capacitor is discharged through a 1.5k
resistor (Human body model)
RECOMMENDED OPERATING
CONDITIONS
Characteristics
Symbol
Min
Typ
Max
Unit
Supply voltage
AVDD33A1
AVDD33A2
3.0
3.3
3.6
V
Reference input voltage
VREF
AGND
2.0
0.0
3.3
0.0
3.6
0.0
V
Analog input voltage
AINT
0.0
VREF
V
Operating temperature
Toper
45
80
C
NOTE: It
is
strongly
recommended
that
all
the
supply
pins
(AVDD33A1,
AVDD33A2)
be
powered
from
the
same
source
to
avoid
power
latch-up.
ADC1395X
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m 10-BIT 500KSPS ADC
6
DC ELECTRICAL
CHARACTERISTICS
Characteristics
Symbol
Min
Typ
Max
Unit
Test Condition
Differential nonlinearity
DNL
0.8
1
LSB
VREF = 3.3V
AGND = 0.0V
Integral nonlinearity
INL
1.0
2
LSB
VREF = 3.3V
AGND = 0.0V
Offset voltage
OFF
3
8
LSB
VREF = 3.3V
AGND = 0.0V
NOTE: (Converter
Specifications
:
AVDD33A1=AVDD33A2=3.3V,
AVSS33A1=AVSS33A2=0V,
Toper=25
C,
VREF=3.3V,
AGND=0.0V
unless
otherwise
specified)
AC ELECTRICAL CHARACTERISTICS
Characteristics
Symbol
Min
Typ
Max
Unit
Test Condition
Maximum conversion rate
fc
500
KSPS
f
CKIN
= 2.5MHz
Standby supply current
10
40
uA
STBY = VDD
Dynamic supply current
IVDD
2.0
3
mA
f
CKIN
= 2.5MHz
(without system load)
Reference current
IREF
0.4
0.6
mA
VREF = 3.3V
Total harmonic distortion
THD
60
dB
f
CKIN
= 2.5MHz
AINT = 100kHz
Signal-to-noise & distortion
Ratio
SNDR
48
54
dB
f
CKIN
= 2.5MHz
AINT = 100kHz
NOTE: (Converter
Specifications
:
AVDD33A1=AVDD33A2=3.3V,
AVSS33A1=AVSS33A2=0V,
Toper=25
C,
VREF=3.3V,
AGND=0.0V
unless
otherwise
specified)
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m 10-BIT 500KSPS ADC
ADC1395X
7
I/O CHART
Index
AINT Input (V)
Digital Output
0
~ 0.00322
00 0000 0000
1LSB=3.22mV
1
0.00322 ~ 0.00644
00 0000 0001
VREF=3.3V
2
0.00644 ~ 0.00967
00 0000 0010
AGND=0.0V
~
~
~
511
1.64678 ~ 1.65000
01 1111 1111
512
1.65000 ~ 1.65322
10 0000 0000
513
1.65322 ~ 1.65644
10 0000 0001
~
~
~
1021
3.29033 ~ 3.29355
11 1111 1101
1022
3.29355 ~ 3.29678
11 1111 1110
1023
3.29678 ~
11 1111 1111
ADC1395X
0.13

m 10-BIT 500KSPS ADC
8
TIMING DIAGRAM
1. Main Waveform
STBY
STC
DO[9:0]
CKIN
Input Sampling Period
AINT
EOC
1
2
3
4
5
A
D
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m 10-BIT 500KSPS ADC
ADC1395X
9
2. STC & CKIN Condition
10ns
CKIN
STC
3ns
T
SAFE
The A/D Converter operates data conversion when STC (Start Conversion) signal is just "HIGH". Otherwise,
output data (DO[9:0]) keep the current states. The STC signal should be changed during "T
SAFE
" with the "HIGH"
level of the clock to operation as shown in the main waveform.
ADC External Interface Signal
-- AINT: Analog Input Signal (Input)
Input Range: VREF ~ AGND
-- STBY: Stand-by Signal, Power Save Mode (Input)
-- CKIN: ADC Main Clock, f
CKIN
= 2.5MHz, 1 Clock Period = 400ns (Input)
-- STC: Start of Conversion Signal (Input)
-- EOC: End of Conversion Signal (Output)
-- DO[9:0]: Digital Output Signal (Output)
ADC1395X
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m 10-BIT 500KSPS ADC
10
CORE EVALUATION GUIDE
ADC function is evaluated by external check on the bi-directional pads connected to input nodes of HOST DSP
back-end circuit.
The reference voltages may be biased internally through resistor divider.
STBY
CKIN
AINT
VREF
AGND
AVDD33A
AVSS33A
AVBB33A
AVDD33D
AVSS33D
[MSB:LSB]
STC
DO[9:0]
EOC
Digital
Mux
HOST
DSP
CORE
Bi-directional
PAD
D[9:0]
D[9:0]
D[9:0]
(ADC Function Test & Externally
forced Digital Input)
adc1395x
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m 10-BIT 500KSPS ADC
ADC1395X
11
PACKAGE CONFIGURATION
adc1395x
48
47
VREF
VREF
AGND
AGND
NC
AVDD33A
AVDD33A
AVBB33A
AVSS33A
AVSS33A
AINT
NC
NC
NC
NC
NC
STBY
VDDR
VSSR
CKIN
NC
NC
NC
RP
AVDD33D
AVDD33D
AVSS33D
AVDD33D
NC
STC
EOC
NC
NC
DO[7]
DO[6]
DO[5]
DO[4]
DO[3]
DO[2]
DO[1]
DO[0]
TEST
TEST
NC
RN
10u
0.1u
10u
Digital I
Digital II
Analog
NC
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
0.1u
10u
0.1u
0.1u
10u
10u 0.1u
10u 0.1u
DO[9]
DO[8]
NOTE: NC denotes "No Connection".
ADC1395X
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m 10-BIT 500KSPS ADC
12
PACKAGE PIN DESCRIPTION
Name
No.
I/O Type
Pin Description
VREF
1, 2
AI
Reference voltage (3.3V)
AGND
3, 4
AI
Analog ground (0.0V)
AVDD33A1
6, 7
AP
Analog power (3.3V)
AVBB33A1
8
AG
Analog sub bias
AVSS33A1
9, 10
AG
Analog ground
AINT
11
AI
Analog input
STBY
17
DI
VDD = Power saving (standby),
GND = Normal
VDDR
18
PP
PAD power (3.3V)
VSSR
19
PG
PAD ground
CKIN
20
DI
Clock input (f
CKIN
= 2.5MHz)
RP
24
AO
Test pin1
RN
25
AO
Test pin2
DO[0]
29
DO
Digital output (LSB)
DO[1:8]
30 ~ 37
DO
Digital output
DO[9]
38
DO
Digital output (MSB)
EOC
41
DO
End of conversion signal
STC
42
DI
Start of conversion signal
AVSS33A2
45, 46
DG
Digital GND
AVSS33A2
47, 48
DP
Digital power (3.3V)
NOTE: I/O
TYPE
PP
and
PG
denote
PAD
Power
and
PAD
Ground
respectively.
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m 10-BIT 500KSPS ADC
ADC1395X
13
CONFIGURATION
VREF
VBBA
NC
NC
NC
RP
adc1395x
VREF
AGND
NC
VDDA
VDDA
VSSA
VSSA
AINT
NC
NC
NC
NC
NC
STBY
VDDR
VSSR
CKIN
VDDD
VDDD
VSSD
VSSD
NC
STC
EOC
NC
NC
DO[7]
DO[6]
DO[5]
DO[4]
DO[3]
DO[2]
DO[1]
DO[0]
TEST
TEST
NC
RN
AGND
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DO[9]
DO[8]
ADC1395X
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m 10-BIT 500KSPS ADC
14
PHANTOM CELL INFORMATION
Pins of the core can be assigned externally (Package pins) or internally (internal ports) depending on design
methods.
--
The term "External" implies that the pins should be assigned externally like power pins.
--
The term "External/internal" implies that the applications of these pins depend on the user.
Pin Name
Pin Usage
Pin Layout Guide
AVDD18A
External
Maintain the large width of lines as far as the pads.
AVSS18A
External
Place the port positions to minimize the length of power lines.
AVBB18A
External
Do not merge the analog powers with anoter power from other
blocks.
AVDD18A
External
Use good power and ground source on board.
AVSS18D
External
AVBB18D
External
AINT
External / Internal
Do not overlap with digital lines.
AINC
External / Internal
Maintain the shotest path to pads.
CKIN
External / Internal
Separate from all other analog signals
REFTOP
External / Internal
Maintain the larger width and the shorter length as far as the
pads.
REFBOT
External / Internal
Separate from all other digital lines.
CML
External / Internal
ITEST
External / Internal
STBY
External / Internal
STC
External / Internal
SPEEDUP
External / Internal
EOC
External / Internal
Separated from the analog clean signals if possible.
DO[9]
External / Internal
Do not exceed the length by 1,000um.
DO[8]
External / Internal
DO[7]
External / Internal
DO[6]
External / Internal
DO[5]
External / Internal
DO[4]
External / Internal
DO[3]
External / Internal
DO[2]
External / Internal
DO[1]
External / Internal
DO[0]
External / Internal
0.13

m 10-BIT 500KSPS ADC
ADC1395X
15
adc1395x
10-bit 500K adc
DO[0]
DO[1]
DO[2]
STC
CKIN
ECO
AVDD33A
AVBB33A
AVSS33A
AGND
VREF
AVDD33D
AVBB33A
AINT
DO[3]
DO[4]
DO[5]
DO[6]
DO[7]
DO[8]
DO[9]
AVSS33D
STBY
ADC1395X
0.13

m 10-BIT 500KSPS ADC
16
USER GUIDE
1. Input Range
The analog input is single-ended type and the range is from VREF to AGND. This AINT voltage follows reference
voltage range fundamentally. So, if you want to alter into the another input range, you should change the voltage
value of VREF.
You can use the AINT voltage whose minimum range is 2.0V. In this case, the VREF is 2.0V.
0.13

m 10-BIT 500KSPS ADC
ADC1395X
17
FEEDBACK
REQUEST
It should be quite helpful to our ADC core development if you specify your system requirements on ADC in the
following characteristic checking table and fill out the additional questions.
We appreciate your interest in our products. Thank you very much.
Characteristic
Min
Typ
Max
Unit
Remarks
Analog power supply voltage
V
Digital power supply voltage
V
Bit resolution
Bit
Reference input voltage
V
Analog input voltage
Vpp
Operating temperature
C
Integral non-linearity error
LSB
Differential non-linearity error
LSB
Bottom offset voltage error
mV
Top offset voltage error
mV
Maximum conversion rate
MSPS
Dynamic supply current
mA
Power dissipation
mW
Signal-to-noise ratio
dB
Pipeline delay
CLK
Digital output format
(Provide detailed description &
timing diagram)
1. Between single input-output and differential input-output configurations, which one is suitable for your system
and why?
2. Please comment on the internal/external pin configurations you want our ADC to have, if you have any reason
to prefer some type of configuration.
3. Freely list those functions you want to be implemented in our ADC, if you have any.
ADC1395X
0.13

m 10-BIT 500KSPS ADC
18
HISTORY CARD
Version
Date
Modified Items
Comments
Ver1.0
02. 04.18
Original version published (preliminary)
Ver1.1
0..04.20
Feedback request is changed.
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