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Datasheet: adc1341x_pc (Samsung semiconductor)

ADC1341X_PC 0.13µm 8-Channel 10-BIT 500KSPS ADC ; Function = ADC ; Configuration = 10BIT 500KSPS ; Library Type = - ; Characteristic = -

 

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Samsung semiconductor
ADC1341X_PC
0.13

m 8-CHANNEL 10-BIT 500KSPS ADC
1
GENERAL DESCRIPTION
The adc1341x_pc is a CMOS 3.3V 10-bit analog-to-digital converter (ADC). It converts the analog input signal
into 10-bit binary digital codes at a maximum conversion rate of 500KSPS with 2.5MHz clock.
The device is a recycling type monolithic ADC with an on-chip sample-and-hold function. The ADC has power
down mode.
FEATURES
-- Resolution: 10-bit
-- Maximum conversion rate: 500KSPS
-- Main clock: 2.5MHz (max.)
-- Power supply: 3.3V
0.3V
-- Total current: 20uA (Standby Mode)
2.5mA (Normal Operation)
-- Input range: 0.0V ~ 3.3V (3.3V
P-P
)
-- Differential linearity error:
1.0 LSB
-- Integral linearity error:
2.0 LSB
-- Signal to noise & distortion ratio: 54dB (Typ.)
-- Digital output: CMOS level
-- Operating temperature range: 40
C ~ 85
C
TYPICAL APPLICATIONS
-- MICOM interface
-- Portable equipment
-- Low-power application
0.13

m 8-CHANNEL 10-BIT 500KSPS ADC
ADC1341X_PC
2
FUNCTIONAL BLOCK DIAGRAM
CLOCK
GEN
AIN[7:0]
VREF
AGND
DO[9:0]
STC
CKIN
STBY
CML
GEN
REF
GEN
MAIN
BIAS
FLASH2
FLASH1
Digital Logic
EOC
MDAC1
MDAC2
ANALOG
MUX
SEL[2:0]
Level
Shift
3.3V
1.2V
Ver 1.0 (Apr. 2002)
This data sheet is a preliminary version. No responsibility is assumed by SEC for its use nor for any infringements of patents
or other rights of third parties that may result from its use. The content of this data sheet is subject to change without any
notice.
ADC1341X_PC
0.13

m 8-CHANNEL 10-BIT 500KSPS ADC
3
CORE PIN DESCRIPTION
Name
I/O Type
I/O Pad
Pin Description
VREF
AI
phia_abb
Reference top (3.3V)
AGND
AI
phia_abb
Reference bottom (0.0V)
AVDD33A1
AP
vdd3t_abb
Analog power (3.3V)
AVBB33A1
AG
vbb3_abb
Analog sub bias (0.0V)
AVSS33A1
AG
vss3t_abb
Analog ground (0.0V)
AIN[7:0]
AI
phiar50_abb
Analog input (input range: 0.0V ~ 3.3V)
SEL[2:0]
DI
picc_abb
Analog input selection pin
STBY
DI
picc_abb
VDD = Power saving (standby),
GND = Normal
CKIN
DI
picc_abb
Sampling clock input
D[9:0]
DO
pot6_abb
Digital output
EOC
DO
pot6_abb
End of conversion signal
STC
DI
picc_abb
Start of conversion signal
AVSS33A2
DG
vss3t_abb
Digital GND (0.0V)
AVDD33A2
DP
vdd3t_abb
Digital power (3.3V)
AVDD12
DP
vdd1t_abb
Digital power (1.2V)
I/O
Type
Abbr.
-- AI: Analog Input
-- DI: Digital Input
-- AO: Analog Output
-- DO: Analog Output
-- AP: Analog Power
-- AG: Analog Ground
-- DP: Digital Power
-- DG: Digital Ground
-- AB: Analog Bi-Direction
-- DB: Digital Bi-Direction
0.13

m 8-CHANNEL 10-BIT 500KSPS ADC
ADC1341X_PC
4
CORE CONFIGURATION
STBY
CKIN
AIN[7:0]
VREF
AGND
AVDD33A1
AVSS33A1
AVBB33A1
AVSS33A2
AVDD12
[MSB:LSB]
STC
DO[9:0]
EOC
SEL[2:0]
AVDD33A2
adc1341x_pc
ADC1341X_PC
0.13

m 8-CHANNEL 10-BIT 500KSPS ADC
5
ABSOLUTE MAXIMUM RATINGS
Characteristics
Symbol
Value
Unit
Supply voltage
VDD33
3.8
V
Analog input voltage
AINT
VSS to VDD
V
Digital input voltage
CKIN
VSS to VDD
V
Reference voltage
VREF / AGND
VSS to VDD
V
Storage temperature range
Tstg
45 to 150
C
Operating temperature range
Topr
40 to 85
C
NOTES:
1.
Absolute
maximum
rating
specifies
the
values
beyond
which
the
device
may
be
damaged
permanently.
Exposure
to
absolute
maximum
rating
conditions
for
extended
periods
may
affect
reliability.
Each
condition
value
is
applied
with
the
other
values
kept
within
the
following
operating
conditions
and
function
operation
under
any
of
these
conditions
is
not
implied.
2.
All
voltages
are
measured
with
respect
to
VSS
unless
otherwise
specified.
3.
100pF
capacitor
is
discharged
through
a
1.5k
resistor
(Human
body
model)
RECOMMENDED OPERATING
CONDITIONS
Characteristics
Symbol
Min
Typ
Max
Unit
Supply voltage
AVDD33A1
AVDD33A2
3.0
3.3
3.6
V
Reference input voltage
VREF
AGND
2.0
0.0
3.3
0.0
3.6
0.0
V
Analog input voltage
AINT
0.0
VREF
V
Operating temperature
Toper
40
85
C
NOTE: It is strongly recommended that all the supply pins (AVDD33A1, AVDD33A2) be powered from the same source to
avoid power latch-up.
DC ELECTRICAL
CHARACTERISTICS
Characteristics
Symbol
Min
Typ
Max
Unit
Test Condition
Differential nonlinearity
DNL
0.8
1
LSB
VREF = 3.3V
AGND = 0.0V
Integral nonlinearity
INL
1.0
2
LSB
VREF = 3.3V
AGND = 0.0V
Offset voltage
TOPOFF
BOTOFF
3
8
LSB
VREF = 3.3V
AGND = 0.0V
(Converter
Specifications
:
AVDD33A1=AVDD33A2=3.3V,
AVDD12=1.2V, AVSS33A1=AVSS33A2=0V,
Toper=25
C,
VREF=3.3V,
AGND=0.0V
unless
otherwise
specified)
0.13

m 8-CHANNEL 10-BIT 500KSPS ADC
ADC1341X_PC
6
AC ELECTRICAL
CHARACTERISTICS
Characteristics
Symbol
Min
Typ
Max
Unit
Test Condition
Maximum conversion rate
fc
500
KSPS
f
CKIN
= 2.5MHz
Standby supply current
20
40
uA
STBY = VDD
Dynamic supply current
IVDD
2.3
3
mA
f
CKIN
= 2.5MHz
(without system load)
Reference current
IREF
0.4
0.6
mA
V
REF
= 3.3V
Total harmonic distortion
THD
60
56
dB
f
CKIN
= 2.5MHz
AINT = 100kHz
Signal-to-noise & distortion
Ratio
SNDR
50
54
dB
f
CKIN
= 2.5MHz
AINT = 100kHz
(Converter
Specifications
:
AVDD33A1=AVDD33A2=3.3V, AVDD12=1.2V,
AVSS33A1=AVSS33A2=0V, Toper=25
C,
VREF=3.3V,
AGND=0.0V
unless
otherwise
specified)
I/O
CHART
Index
AINT Input (V)
Digital Output
0
~ 0.00322
00 0000 0000
1LSB = 3.22mV
1
0.00322 ~ 0.00644
00 0000 0001
VREF = 3.3V
2
0.00644 ~ 0.00967
00 0000 0010
AGND = 0.0V
~
~
~
511
1.64678 ~ 1.65000
01 1111 1111
512
1.65000 ~ 1.65322
10 0000 0000
513
1.65322 ~ 1.65644
10 0000 0001
~
~
~
1021
3.29033 ~ 3.29355
11 1111 1101
1022
3.29355 ~ 3.29678
11 1111 1110
1023
3.29678 ~
11 1111 1111
ADC1341X_PC
0.13

m 8-CHANNEL 10-BIT 500KSPS ADC
7
TIMING DIAGRAM
1. Main Waveform
STBY
STC
DO[9:0]
CKIN
Input Sampling Period
AIN[7:0]
EOC
A2
1
2
3
4
5
A1
SEL[2:0]
2. STC & CKIN Condition
10ns
CKIN
STC
3ns
T
SAFE
The A/D Converter operates data conversion when STC (Start Conversion) signal is just "HIGH". Otherwise,
output data (DO[9:0]) keep the current states. The STC signal should be changed during "TSAFE" with the
"HIGH" level of the clock to operation as shown in the main waveform.
0.13

m 8-CHANNEL 10-BIT 500KSPS ADC
ADC1341X_PC
8
3. SEL[2:0] & CKIN Condition
10ns
CKIN
SEL[2:0]
10ns
The transition of SEL[2:0] signals should be synchronized with the falling edge of CKIN signal.
This ADC samples analog input signal at the first low state of CKIN after rising transition of STC.
So you should keep in mind that a proper channel should be selected by SEL[2:0] before sampling the analog
input signal.
ADC1341X_PC
0.13

m 8-CHANNEL 10-BIT 500KSPS ADC
9
CORE EVALUATION GUIDE
ADC function is evaluated by external check on the bi-directional pads connected to input nodes of HOST DSP
back-end circuit.
The reference voltages may be biased internally through resistor divider.
STBY
CKIN
AIN[7:0]
VREF
AGND
AVDD33A1
AVSS33A1
AVBB33A1
AVDD33A2
AVDD12
[MSB:LSB]
STC
DO[9:0]
EOC
Digital
Mux
HOST
DSP
CORE
Bi-directional
PAD
D[9:0]
D[9:0]
D[9:0]
(ADC Function Test & Externally
Forced Digital Input)
SEL[2:0]
AVDD33A2
adc1341x_pc
0.13

m 8-CHANNEL 10-BIT 500KSPS ADC
ADC1341X_PC
10
USER GUIDE
Input Range
The analog input is single-ended type and the range is from VREF to AGND. This AINT voltage follows reference
voltage range fundamentally. So, if you want to alter into the another input range, you should change the voltage
value of VREF.
You can use the AINT voltage whose minimum range is 2.0V. In this case, the VREF is 2.0V.
ANALOG INPUT SELECTION TABLE
AIN[7]
AIN[6]
AIN[5]
AIN[4]
AIN[3]
AIN[2]
AIN[1]
AIN[0]
SEL[2]
1
1
1
1
0
0
0
0
SEL[1]
1
1
0
0
1
1
0
0
SEL[0]
1
0
1
0
1
0
1
0
ADC1341X_PC
0.13

m 8-CHANNEL 10-BIT 500KSPS ADC
11
PHANTOM CELL INFORMATION
DO[8]
DO[0]
DO[4]
DO[2]
DO[3]
DO[5]
DO[6]
DO[7]
DO[1]
STC
CKIN
EOC
AVDD33A2
AVBB33A1
AVSS33A2
STBY
VREF
AGND
AVSS33A1
AVBB33A1
AVDD33A1
adc1341x_pc
DO[9]
AIN[0]
ENB
EN
AVDD12
AIN[7]
AIN[1]
SEL[0]
SEL[1]
SEL[2]
.
.
.
.
.
0.13

m 8-CHANNEL 10-BIT 500KSPS ADC
ADC1341X_PC
12
Name
I/O Type
Pin Usage
Pin Description
AIN[7:0]
AI
Internal/External
AIN[7:0] signal should not be crossed by any signals
and should not run next to digital signals to minimize
capacitive coupling between the two signals.
SEL[2:0]
DI
Internal/External
Digital Input Signal lines must have same length to
reduce
propagation delay.
STBY
DI
Internal/External
CKIN
DI
Internal/External
D[9:0]
DO
Internal/External
EOC
DO
Internal/External
STC
DI
Internal/External
VREF
AI
External
Voltage reference lines (VREF and AGND) must be wide
metal to reduce voltage drop of metal lines.
AGND
AI
External
AVDD33A1
AP
External
It is recommended that you use thick analog power
metal. When connected to PAD, the path should be kept
as short as possible.
AVBB33A1
AG
External
Digital power and analog power are separately used.
AVSS33A1
AG
External
AVSS33A2
DG
External
AVDD33A2
DP
External
AVDD12
DP
External
EN
DI
Internal
EN, ENB are special function pin.
ENB
DI
Internal
Actually, EN = VDD (1.2V or 3.3V), ENB = VSS
ADC1341X_PC
0.13

m 8-CHANNEL 10-BIT 500KSPS ADC
13
FEEDBACK
REQUEST
It should be quite helpful to our ADC core development if you specify your system requirements on ADC in the
following characteristic checking table and fill out the additional questions.
We appreciate your interest in our products. Thank you very much.
Parameter
Min
Typ
Max
Unit
Remarks
Analog power supply voltage
V
Digital power supply voltage
V
Bit resolution
Bit
Reference input voltage
V
Analog input voltage
Vpp
Operating temperature
C
Integral non-linearity error
LSB
Differential non-linearity error
LSB
Bottom offset voltage error
mV
Top offset voltage error
mV
Maximum conversion rate
MSPS
Dynamic supply current
mA
Power dissipation
mW
Signal-to-noise ratio
dB
Digital output format (provide detailed
description & timing diagram)
-- Between single input-output and differential input-output configurations, which one is suitable for your system
and why?
-- Please comment on the internal/external pin configurations you want our ADC to have, if you have any
reason to prefer some type of configuration.
-- Freely list those functions you want to be implemented in our ADC, if you have any.
0.13

m 8-CHANNEL 10-BIT 500KSPS ADC
ADC1341X_PC
14
HISTORY CARD
Version
Date
Modified Items
Comments
Ver1.0
02. 04. 27
Original version published (preliminary)
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