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Datasheet: adc1275x_pc (Samsung semiconductor)

ADC1275X_PC 0.18µm 10-BIT 500KSPS ADC ; Function = ADC ; Configuration = 10BIT 500KSPS ; Library Type = - ; Characteristic = -

 

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Samsung semiconductor
ADC1275X_PC
0.18
m 10-BIT 500KSPS ADC
1
GENERAL DESCRIPTION
The ADC1275X_PC is a CMOS 3.3V 10-bit analog-to-digital converter (ADC). It converts the analog input signal into
10-bit binary digital codes at a maximum conversion rate of 500KSPS with 2.5MHz clock.
The device is a recycling type monolithic ADC with an on-chip sample-and-hold function. The ADC has power down
mode.
FEATURES
-- Resolution : 10-bit
-- Maximum Conversion Rate : 500KSPS
-- Main Clock : 2.5MHz (Max.)
-- Power Supply : 3.3V
0.3V
-- Total Current : 1uA (Standby Mode)
1.5mA (Normal Operation)
-- Input Range : 0.0V 3.3V (3.3V
P-P
)
-- Differential Linearity
Error :
1.0 LSB (Max)
-- Integral Linearity Error :
2.0 LSB (Max.)
-- Signal to Noise & Distortion Ratio : 56dB (Typ.)
-- Digital Output : CMOS Level
-- Operating Temperature Range : -40
C 85
C
TYPICAL APPLICATIONS
-- Micom Interface
-- Portable Equipment
-- Low-Power Application
0.18
m 10-BIT 500KSPS ADC
ADC1275X_PC
2
FUNCTIONAL BLOCK DIAGRAM
AIN[7:0]
VREF
AGND
DO[9:0]
EOC
STC
CKIN
STBY
MAIN
BIAS
REF
GEN
CML
GEN
CLOCK
GEN
MDAC1
FLASH1
MDAC2
FLASH2
DIGITAL
LOGIC
Level
Shifter
3.3V 1.8V
ANALOG
MUX
SEL[2:0]
Ver 1.5 (Mar. 2003)
No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties
that may result from its use. The content of this data sheet is subject to change without any notice.
ADC1275X_PC
0.18
m 10-BIT 500KSPS ADC
3
CORE PIN DESCRIPTION
Name
I/O Type
I/O Pad
Pin Description
VREF
AI
phia_abb
Reference Top (3.3V)
AGND
AI
phia_abb
Reference Bottom (0.0V)
AVDD33A1
AP
vdd3t_abb
Analog Power (3.3V)
AVBB33A1
AG
vbb3_abb
Analog Sub Bias (0.0V)
AVSS33A1
AG
vss3t_abb
Analog Ground (0.0V)
AIN[7:0]
AI
phiar50_abb
Analog Input
(Input Range : 0.0V ~ 3.3V)
SEL[2:0]
DI
picc_abb
Analog Input Selection Pin
STBY
DI
picc_abb
V
DD
=power saving (standby),
GND=normal
CKIN
DI
picc_abb
Sampling Clock Input
D[9:0]
DO
pot4_abb
Digital Output
EOC
DO
pot4_abb
End of Conversion Signal
STC
DI
picc_abb
Start of Conversion Signal
AVSS33A2
DG
vss3t_abb
Digital GND (0.0V)
AVDD33A2
DP
vdd3t_abb
Digital Power (3.3V)
AVDD18
DP
vdd1t_abb
Digital Power (1.8V)
I/O Type Abbr.
-- AI: Analog Input
-- DI: Digital Input
-- AO: Analog Output
-- DO: Digital Output
-- AP: Analog Power
-- AG: Analog Ground
-- DP: Digital Power
-- DG: Digital Ground
-- AB: Analog Bi-direction
-- DB: Digital Bi-direction
0.18
m 10-BIT 500KSPS ADC
ADC1275X_PC
4
[MSB:LSB]
adc1275x_pc
AGND
VREF
AIN[7:0]
CKIN
STBY
SEL[2:0]
DO[9:0]
EOC
STC
AVDD33A1
AVSS33A1
AVSS33A2
AVDD18
AVBB33A1
AVDD33A2
ADC1275X_PC
0.18
m 10-BIT 500KSPS ADC
5
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Value
Unit
Supply Voltage
VDD33
3.8
V
Analog Input Voltage
AINT
V
SS
to V
DD
V
Digital Input Voltage
CKIN
V
SS
to V
DD
V
Reference Voltage
VREF/AGND
V
SS
to V
DD
V
Storage Temperature Range
Tstg
-45 to 150
C
Operating Temperature Range
Topr
-40 to 85
C
NOTES:
1. Absolute maximum rating specifies the values beyond which the device may be damaged permanently. Exposure to
ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied
with the other values kept within the following operating conditions and function operation under any of these conditions
is not implied.
2. All voltages are measured with respect to V
SS
unless otherwise specified.
3. 100pF capacitor is discharged through a 1.5K
resistor (Human body model)
RECOMMENDED OPERATING CONDITIONS
Characteristics
Symbol
Min
Typ
Max
Unit
Supply Voltage
AVDD33A1
AVDD33A2
3.0
3.3
3.6
V
Reference Input Voltage
VREF
AGND
2.0
0.0
3.3
0.0
3.6
0.0
V
Analog Input Voltage
AINT
0.0
VREF
V
Operating Temperature
Toper
-40
85
C
NOTE: It is strongly recommended that all the supply pins (AVDD33A1, AVDD33A2) be powered from the same source to
avoid power latch-up.
DC ELECTRICAL CHARACTERISTICS
Characteristics
Symbol
Min
Typ
Max
Unit
Test Conditions
Differential Nonlinearity
DNL
0.8
1
LSB
VREF=3.3V
AGND=0.0V
Integral Nonlinearity
INL
1.0
2
LSB
VREF=3.3V
AGND=0.0V
Offset Voltage
TOPOFF
BOTOFF
3
8
LSB
VREF=3.3V
AGND=0.0V
(Converter Specifications : AVDD33A1=AVDD33A2=3.3V,
AVDD18=1.8V, AVSS33A1=AVSS33A2=0V,
Toper=25
C,
VREF=3.3V,
AGND=0.0V
unless
otherwise
specified)
0.18
m 10-BIT 500KSPS ADC
ADC1275X_PC
6
AC ELECTRICAL CHARACTERISTICS
Characteristics
Symbol
Min
Typ
Max
Unit
Test Conditions
Maximum Conversion Rate
fc
500
KSPS
f
CKIN
= 2.5 MHz
Standby Supply Current
1
10
uA
STBY = V
DD
Dynamic Supply Current
IVDD
1.5
2
mA
f
CKIN
= 2.5 MHz
(without system load)
Reference Current
IREF
0.25
0.5
mA
V
REF
= 3.3V
Total Harmonic Distortion
THD
-60
-56
dB
f
CKIN
= 2.5 MHz
AINT = 100 kHz
Signal-to-Noise & Distortion
Ratio
SNDR
50
56
dB
f
CKIN
= 2.5 MHz
AINT = 100 kHz
(Converter Specifications : AVDD33A1=AVDD33A2=3.3V, AVSS33A1=AVSS33A2=0V, Toper=25
C, VREF=3.3V,
AGND=0.0V unless otherwise specified)
I/O
CHART
Index
AINT Input (V)
Digital Output
0
~ 0.00322
00 0000 0000
1LSB = 3.22mV
1
0.00322 ~ 0.00644
00 0000 0001
VREF
= 3.3V
2
0.00644 ~ 0.00967
00 0000 0010
AGND = 0.0V
511
1.64678 ~ 1.65000
01 1111 1111
512
1.65000 ~ 1.65322
10 0000 0000
513
1.65322 ~ 1.65644
10 0000 0001
1021
3.29033 ~ 3.29355
11 1111 1101
1022
3.29355 ~ 3.29678
11 1111 1110
1023
3.29678 ~
11 1111 1111
ADC1275X_PC
0.18
m 10-BIT 500KSPS ADC
7
TIMING DIAGRAM
1. Main Waveform
AIN[7:0]
1
2
3
4
5
A1
A2
Input Sampling Period
CKIN
SEL[20]
STBY
STC
EOC
DO[9:0]
2. STC & CKIN Condition
CKIN
STC
T
SAFE
10ns
3ns
The A/D Converter operates data conversion when STC (Start Conversion) signal is just "HIGH". Otherwise, output
data (DO[9:0]) keep the current states. The STC signal should be changed during "T
SAFE
" with the "HIGH" level of
the clock to operation as shown in the main waveform.
3. SEL[2:0] & CKIN Condition
CKIN
SEL[2:0]
10ns
10ns
The transition of SEL[2:0] signals should be synchronized with the falling edge of CKIN signal. This ADC samples
analog input signal at the first low state of CKIN after rising transition of STC. So you should keep in mind that a
proper channel should be selected by SEL[2:0] before sampling the analog input signal.
0.18
m 10-BIT 500KSPS ADC
ADC1275X_PC
8
CORE EVALUATION GUIDE
1. ADC function is evaluated by external check on the bidirectional pads connected to input nodes of HOST DSP
back-end circuit.
2. The reference voltages may be biased internally through resistor divider.
[MSB:LSB]
DO[9:0]
EOC
Digital MUX
D[9:0]
D[9:0]
Host
DSP
Core
D[9:0]
Bidirectional
PAD
(ADC Function Test &
externally forced Digital Input)
[MSB:LSB]
adc1275x_pc
AGND
VREF
AIN[7:0]
CKIN
STBY
SEL[2:0]
STC
AVDD33A1
AVSS33A1
AVSS33A2
AVDD18
AVBB33A1
AVDD33A2
ADC1275X_PC
0.18
m 10-BIT 500KSPS ADC
9
USER GUIDE
Input Range
-- The analog input is single-ended type and the range is from VREF to AGND. This AINT voltage follows
reference voltage range fundamentally. So, if you want to alter into the another input range, you should change
the voltage value of VREF.
-- You can use the AINT voltage whose minimum range is 2.0V. In this case, the VREF is 2.0V.
INPUT SELECTION TABLE
AIN[7]
AIN[6]
AIN[5]
AIN[4]
AIN[3]
AIN[2]
AIN[1]
AIN[0]
SEL[2]
1
1
1
1
0
0
0
0
SEL[1]
1
1
0
0
1
1
0
0
SEL[0]
1
0
1
0
1
0
1
0
0.18
m 10-BIT 500KSPS ADC
ADC1275X_PC
10
PHANTOM CELL INFORMATION
DO[9]
DO[8]
DO[0]
DO[4]
DO[2]
DO[3]
DO[5]
DO[6]
DO[7]
DO[1]
STC
CKIN
EOC
AVDD18
AVDD33A2
AVBB33A1
AVSS33A2
STBY
VREF
AGND
AVSS33A1
AVBB33A1
AVDD33A1
SEL[0]
AIN[0]
SEL[2]
AIN[1]
AIN[7]
SEL[1]
adc1275x_pc
ENB
EN
ADC1275X_PC
0.18
m 10-BIT 500KSPS ADC
11
Pin Name
I/O Type
Pin Usage
Pin Description
AIN[7:0]
AI
Internal/External AIN[7:0] signal should not be crossed by any signals and should
not run next to digital signals to minimize capacitive coupling
between the two signals.
SEL[2:0]
DI
Internal/External Digital Input Signal lines must have same length to reduce
STBY
DI
Internal/External propagation delay.
CKIN
DI
Internal/External
D[9:0]
DO
Internal/External
EOC
DO
Internal/External
STC
DI
Internal/External
VREF
AI
External
Voltage reference lines (VREF and AGND) must be wide
AGND
AI
External
metal to reduce voltage drop of metal lines.
AVDD33A1
AP
External
1. It is recommended that you use thick analog power metal.
AVBB33A1
AG
External
When connected to PAD, the path should be kept as short
AVSS33A1
AG
External
as possible.
AVSS33A2
DG
External
2. Digital power and analog power are separately used.
AVDD33A2
DP
External
AVDD18
DP
External
EN
DI
Internal
EN, ENB are special function pin.
ENB
DI
Internal
Actually, EN = V
DD
(1.8V or 3.3V), ENB = V
SS
(0.0V)
0.18
m 10-BIT 500KSPS ADC
ADC1275X_PC
12
FEEDBACK REQUEST
ADC Specification
Parameter
Min
Typ
Max
Unit
Remarks
Supply voltage
V
Reference Input voltage
V
Analog Input voltage
V
PP
Operating temperature
C
Integral non-linearity error
LSB
Differential non-linearity error
LSB
Offset voltage error (Bottom)
mV
Offset voltage error (Top)
mV
Maximum conversion rate
MSPS
Dynamic supply current
mA
Power dissipation
mW
Signal-to-noise ratio
dB
Digital output format
(Provide detailed description & timing diagram)
What do you want to choose as power supply voltages? For example, the analog V
DD
needs to be 5V.
The digital V
DD
can be 3.3V/5V.
What resolution do you need for ADC?
How about conversion speed (data in
data out)?
How many cycles do exist during the latency of ADC (pipelined delay)?
What's the input range? And then what do you need between single input and differential input?
Can the bus interface be compatible with TTL?
Could you explain external/internal pin configurations as required?
Specially requested function list :
ADC1275X_PC
0.18
m 10-BIT 500KSPS ADC
13
HISTORY CARD
Version
Date
Modified Items
Comments
ver 1.0
Original version published (preliminary)
ver 1.1
ver 1.2
ver 1.3
2001.12
Release the formal datasheet
ver 1.4
2002.04
Add the pin information to the phantom cell information
Temperature range is modified
ver 1.5
2003.05
Total current and typical SNDR values are changed.
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