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Datasheet: 62256 (Samsung semiconductor)

32kx8 Bit Low Power Cmos Static Ram

 

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Samsung semiconductor
Revision 4.0
KM62256C Family
CMOS SRAM
December 1997
1
Document Title
32Kx8 bit Low Power CMOS Static RAM
Revision History
Revision No
0.0
0.1
1.0
2.0
3.0
4.0
Remark
Design target
Preliminary
Final
Final
Final
Final
History
Advance information
Initial draft
Finalize
Revise
- Add 45ns part with 30pF test load
Revise
- Change specification format and merge :
Commercial, Extended, Industrial product in same datasheets.
Revise
- Change Speed bin
Erase 45ns part from commercial product and 100ns from
extended and industrial product.
- Production change
Erase Low power product from TSOP package
Draft Data
February 12th 1993
November 2nd 1993
September 24th 1994
August 12th 1995
April 15th 1996
December 19 1997
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications and product. SAMSUNG Electronics will evaluate and reply to your requests and questions about
device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision 4.0
KM62256C Family
CMOS SRAM
December 1997
2
32Kx8 bit Low Power CMOS Static RAM
The KM62256C family is fabricated by SAMSUNG
s advanced
CMOS process technology. The family supports various operat-
ing temperature ranges and has various package types for user
flexibility of system design. The family also support low data
retention voltage for battery back-up operation with low data
retention current.
GENERAL DESCRIPTION
FEATURES
Process Technology : 0.7
m CMOS
Organization : 32Kx8
Power Supply Voltage : Single 5V
10%
Low Data Retention Voltage : 2V(Min)
Three state output and TTL Compatible
Package Type : 28-DIP-600, 28-SOP-450,
28-TSOP1 -0813.4F/R
PIN DESCRIPTION
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
VCC
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
NameName
Function
A
0
~A
14
Address Inputs
WE
Write Enable Input
CS
Chip Select Input
OE
Output Enable Input
I/O
1
~I/O
8
Data Inputs/Outputs
Vcc
Power(5V)
Vss
Ground
28-DIP
28-SOP
15
16
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PRODUCT FAMILY
Product Family
Operating Temperature.
Speed(ns)
PKG Type
Power Dissipation
Standby
(I
SB1
, Max)
Operating
(Icc
2
)
KM62256CL
Commercial (0~70
C)
55/70ns
28-DIP, 28-SOP
28-TSOP I R/F
100
A
70mA
KM62256CL-L
20
A
KM62256CLE
Extended (-25~85
C)
70ns
28-SOP
28-TSOP I R/F
100
A
KM62256CLE-L
50
A
KM62256CLI
Industrial (-40~85
C)
70ns
28-SOP
28-TSOP I R/F
100
A
KM62256CLI-L
50
A
FUNCTIONAL BLOCK DIAGRAM
A11
A9
A8
A13
WE
VCC
A3
A14
A12
A7
A6
A5
A4
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
28-TSOP
Type I - Forward
1
2
3
4
5
6
7
8
9
10
11
12
13
14
27
26
28
25
24
23
22
21
20
19
18
17
16
15
OE
28-TSOP
A11
A9
A8
A13
WE
VCC
A3
A14
A12
A7
A6
A5
A4
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
27
26
28
25
24
23
22
21
20
19
18
17
16
15
OE
Type I - Reverse
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Precharge circuit.
Memory array
512 rows
64
8 columns
I/O Circuit
Column select
Clk gen.
Row
select
A0
A1
A2
A9
A10
A11
A3
A4
A5
A6
A7
A8
A13
CS
WE
I/O
1
Data
cont
Data
cont
OE
I/O
8
A12
A14
Control
Logic
Revision 4.0
KM62256C Family
CMOS SRAM
December 1997
3
PRODUCT LIST
Note : LL means Low Low standby current.
Commercial Temp Product
(0~70
C)
Extended Temp Products
(-25~85
C)
Industrial Temp Products
(-40~85
C)
Part Name
Function
Part Name
Function
Part Name
Function
KM62256CLP-5
KM62256CLP-5L
KM62256CLP-7
KM62256CLP-7L
KM62256CLG-5
KM62256CLG-5L
KM62256CLG-7
KM62256CLG-7L
KM62256CLTG-5L
KM62256CLTG-7L
KM62256CLRG-5L
KM62256CLRG-7L
28-DIP, 55ns, L-pwr
28-DIP, 55ns, LL-pwr
28-DIP, 70ns, L-pwr
28-DIP, 70ns, LL-pwr
28-SOP, 55ns, L-pwr
28-SOP, 55ns, LL-pwr
28-SOP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-TSOP F, 55ns, LL-pwr
28-TSOP F, 70ns, LL-pwr
28-TSOP R, 55ns, LL-pwr
28-TSOP R, 70ns, LL-pwr
KM62256CLGE-7
KM62256CLGE-7L
KM62256CLTGE-7L
KM62256CLRGE-7L
28-SOP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-TSOP F, 70ns, LL-pwr
28-TSOP R, 70ns, LL-pwr
KM62256CLGI-7
KM62256CLGI-7L
KM62256CLTGI-7L
KM62256CLRGI-7L
28-SOP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-TSOP F, 70ns, LL-pwr
28-TSOP R, 70ns, LL-pwr
FUNCTIONAL DESCRIPTION
1. X means don
t care
CS
OE
WE
I/O Pin
Mode
Power
H
X
X
High-Z
Deselected
Standby
L
H
H
High-Z
Output Disabled
Active
L
L
H
Dout
Read
Active
L
X
L
Din
Write
Active
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Item
Symbol
Ratings
Unit
Remark
Voltage on any pin relative to Vss
V
IN
,V
OUT
-0.5 to V
CC
+0.5
V
-
Voltage on Vcc supply relative to Vss
V
CC
-0.5 to 7.0
V
-
Power Dissipation
P
D
1.0
W
-
Storage temperature
T
STG
-65 to 150
C
-
Operating Temperature
T
A
0 to 70
C
KM62256CL
-25 to 85
C
KM62256CLE
-40 to 85
C
KM62256CLI
Soldering temperature and time
T
SOLDER
260
C, 10sec(Lead Only)
-
-
Revision 4.0
KM62256C Family
CMOS SRAM
December 1997
4
RECOMMENDED DC OPERATING CONDITIONS
1)
Note
1. Commercial Product : T
A
=0 to 70
C, unless otherwise specified
Extended Product : T
A
=-25 to 85
C, unless otherwise specified
Industrial Product : T
A
=-40 to 85
C, unless otherwise specified
2. Overshoot : V
CC
+3.0V in case of pulse width
30ns
3. Undershoot : -3.0V in case of pulse width
30ns
4. Overshoot and undershoot is sampled, not 100% tested
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
4.5
5.0
5.5
V
Ground
Vss
0
0
0
V
Input high voltage
V
IH
2.2
-
Vcc+0.5V
2)
V
Input low voltage
V
IL
-0.5
3)
-
0.8
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled, not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
6
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
8
pF
DC AND OPERATING CHARACTERISTICS
1. 20mA for Extended and Industrial Products
2. 10mA for Extended and Industrial Products
3. 2mA for Extended and Industrial Products
Item
Symbol
Test Conditions
Min
Typ
Max Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS=V
IH
or
WE=V
IL
, V
IO
=Vss to Vcc
-1
-
1
A
Operating power supply current
I
CC
I
IO
=0mA, CS=V
IL,
V
IN
=V
IH
or V
IL
-
7
15
1)
mA
Average operating current
I
CC1
Cycle time=1
s, 100% duty, I
IO
=0mA
CS
0.2V, V
IN
0.2V, V
IN
Vcc -0.2V
-
-
7
2)
mA
I
CC2
Cycle time=Min,100% duty, I
IO
=0mA, CS=V
IL,
V
IN
=V
IH
or V
IL
-
-
70
mA
Output low voltage
V
OL
I
OL
=2.1mA
-
-
0.4
V
Output high voltage
V
OH
I
OH
=-1.0mA
2.4
-
-
V
Standby Current(TTL)
I
SB
CS=V
IH
, Other inputs=V
IH
or V
IL
-
-
1
3)
mA
Standby Current
(CMOS)
KM62256CL
KM62256CL-L
I
SB1
CS
Vcc-0.2V,
Other inputs=0~Vcc
L(Low Power)
LL(L Low Power)
-
-
2
1
100
20
A
KM62256CLE
KM62256CLE-L
L(Low Power)
LL(L Low Power)
-
-
-
-
100
50
A
KM62256CLI
KM62256CLI-L
L(Low Power)
LL(L Low Power)
-
-
-
-
100
50
A
Revision 4.0
KM62256C Family
CMOS SRAM
December 1997
5
C
L
1)
1. Including scope and jig capacitance
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falingl time : 5ns
input and output reference voltage : 1.5V
Output load (See right) :C
L
=100pF+1TTL
AC OPERATING CONDITIONS
A
C CHARACTERISTICS
(Vcc=4.5~5.5V, KM62256C Family : T
A
=0 to 70
C, KM62256CE Family : T
A
=-25 to 85
C,
KM62256CI Family : T
A
=-40 to 85
C)
Parameter List
Symbol
Speed Bins
Units
55ns
70ns
Min
Max
Min
Max
Read
Read cycle time
t
RC
55
-
70
-
ns
Address access time
t
AA
-
55
-
70
ns
Chip select to output
t
CO
-
55
-
70
ns
Output enable to valid output
t
OE
-
25
-
35
ns
Chip select to low-Z output
t
LZ
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
ns
Chip disable to high-Z output
t
HZ
0
20
0
30
ns
Output disable to high-Z output
t
OHZ
0
20
0
30
ns
Output hold from address change
t
OH
5
-
5
-
ns
Write
Write cycle time
t
WC
55
-
70
-
ns
Chip select to end of write
t
CW
45
-
60
-
ns
Address set-up time
t
AS
0
-
0
-
ns
Address valid to end of write
t
AW
45
-
60
-
ns
Write pulse width
t
WP
40
-
50
-
ns
Write recovery time
t
WR
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
20
0
25
ns
Data to write time overlap
t
DW
25
-
30
-
ns
Data hold from write time
t
DH
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
ns
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
Vcc-0.2V
2.0
-
5.5
V
Data retention current
I
DR
KM62256CL
KM62256CL-L
Vcc=3.0V
CS
Vcc-0.2V
L-Ver
LL-Ver
-
-
1
0.5
50
10
A
KM62256CLE
KM62256CLE-L
L-Ver
LL-Ver
-
-
-
-
50
25
KM62256CLI
KM62256CLI-L
L-Ver
LL-Ver
-
-
-
-
50
25
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ms
Recovery time
t
RDR
5
-
-
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