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Datasheet: LNK562P (Power Integrations, Inc.)

Energy Effi cient Off-Line Switcher IC for Linear Transformer Replacement

 

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Power Integrations, Inc.
I
O
I
R
V
R
V
O
Rated Output Power = V
R
I
R
PI-3924-011706
LNK562-564
LinkSwitch-LP
Energy Effi cient Off-Line Switcher IC for
Linear Transformer Replacement
Figure 1. Typical Application not a Simplifi ed Circuit (a) and
Output Characteristic Envelope (b).
Product Highlights
Lowest System Cost and Advanced Safety Features
Lowest component count switcher
Very tight parameter tolerances using proprietary IC
trimming technology and transformer construction
techniques enable ClamplessTMdesigns decreases
component count/system cost and increases effi ciency
Meets industry standard requirements for thermal overload
protection eliminates the thermal fuse used with linear
transformers or additional components in RCC designs
Frequency jittering greatly reduces EMI enables low cost
input fi lter confi guration
Meets HV creepage requirements between DRAIN and all
other pins, both on the PCB and at the package
Proprietary
E-ShieldTM transformer eliminates Y capacitor
Superior Performance over Linear and RCC
Hysteretic thermal shutdown protection automatic
recovery improves fi eld reliability
Universal input range allows worldwide operation
Auto-restart reduces delivered power by >85% during
short circuit and open loop fault conditions
Simple ON/OFF control, no loop compensation needed
High bandwidth provides fast turn on with no overshoot
and excellent transient load response
EcoSmart
Energy Effi ciency Technology
Easily meets all global energy effi ciency regulations with
no added components
No-load consumption <150 mW at 265 VAC input
ON/OFF control provides constant effi ciency to very
light loads ideal for mandatory CEC regulations
Applications
Chargers for cell/cordless phones, PDAs, power tools,
MP3/portable audio devices, shavers etc.
Standby and auxiliary supplies
Description
LinkSwitch-LP switcher ICs cost effectively replace all
unregulated isolated linear transformer based (50/60 Hz) power
supplies up to 3 W output power. For worldwide operation, a
single universal input design replaces multiple linear transformer
based designs. The self-biased circuit achieves an extremely low
no-load consumption of under 150 mW. The internal oscillator
Table 1. Notes: 1. Output power may be limited by specifi c application
parameters including core size and Clampless operation (see Key
Application Considerations). 2. Minimum continuous power in a typical
non-ventilated enclosed adapter measured at 50 C ambient. 3. Minimum
practical continuous power in an open frame design with adequate
heat sinking, measured at 50 C ambient. 4. Packages: P: DIP-8B,
G: SMD-8B. For lead-free package options, see Part Ordering
Information.
frequency is jittered to signifi cantly reduce both quasi-peak and
average EMI, minimizing fi lter cost.
October 2005
OUTPUT POWER TABLE
1
PRODUCT
4
230 VAC 15%
85-265 VAC
Adapter
2
Open
Frame
3
Adapter
2
Open
Frame
3
LNK562P or G
1.9 W
1.9 W
1.9 W
1.9 W
LNK563P or G
2.5 W
2.5 W
2.5 W
2.5 W
LNK564P or G
3 W
3 W
3 W
3 W
(a)
(b)
+
D
S
FB
BP
DC
Output
AC
IN
LinkSwitch-LP
PI-3923-092705
2
LNK562-564
F
10/05
Figure 2. Functional Block Diagram.
Pin Functional Description
DRAIN (D) Pin:
The power MOSFET drain connection provides internal
operating current for both start-up and steady-state operation.
BYPASS (BP) Pin:
A 0.1 F external bypass capacitor for the internally generated
5.8 V supply is connected to this pin.
FEEDBACK (FB) Pin:
During normal operation, switching of the power MOSFET is
controlled by this pin. MOSFET switching is disabled when a
current greater than 70 A fl ows into this pin.
SOURCE (S) Pin:
This pin is the power MOSFET source connection. It is also the
ground reference for the BYPASS and FEEDBACK pins.
LinkSwitch-LP
Functional
Description
LinkSwitch-LP comprises a 700 V power MOSFET switch with
a power supply controller on the same die. Unlike conventional
PWM (pulse width modulation) controllers, it uses a simple
ON/OFF control to regulate the output voltage. The controller
consists of an oscillator, feedback (sense and logic) circuit, 5.8 V
regulator, BYPASS pin under-voltage circuit, over-temperature
PI-3491-111903
FB
D
S
BP
S
S
S
P Package (DIP-8B)
G Package (SMD-8B)
8
5
7
1
4
2
3
Figure 3. Pin Confi guration.
protection, frequency jittering, current limit circuit, and leading
edge blanking.
Oscillator
The typical oscillator frequency is internally set to an average
of 66/83/100 kHz for the LNK562, 563 & 564 respectively.
Two signals are generated from the oscillator: the maximum
duty cycle signal (DC
MAX
) and the clock signal that indicates
the beginning of each switching cycle.
PI-3958-092905
CLOCK
JITTER
AUTO-RESTART
COUNTER
FAULT
PRESENT
OSCILLATOR
5.8 V
4.85 V
SOURCE
(S)
S
R
Q
DC
MAX
ADJ
BYPASS
(BP)
+
-
VI
LIMIT
LEADING
EDGE
BLANKING
THERMAL
SHUTDOWN
+
-
DRAIN
(D)
BYPASS PIN
UNDER-VOLTAGE
CURRENT LIMIT
COMPARATOR
FEEDBACK
(FB)
OPEN LOOP
PULLDOWN
Q
6.3 V
1.69 V -V
TH
0.8 V
+
REGULATOR
5.8 V
RESET
3
LNK562-564
F
10/05
The oscillator incorporates circuitry that introduces a small
amount of frequency jitter, typically 5% of the switching
frequency, to minimize EMI. The modulation rate of the
frequency jitter is set to 1 kHz to optimize EMI reduction
for both average and quasi-peak emissions. The frequency
jitter, which is proportional to the oscillator frequency, should
be measured with the oscilloscope triggered at the falling
edge of the DRAIN voltage waveform. The waveform in
Figure 4 illustrates the frequency jitter. The oscillator frequency
is reduced when the FB pin voltage is less than 1.69 V as
described below.
Feedback Input Circuit
The feedback input circuit at the FB pin consists of a low
impedance source follower output set at 1.69 V. When the current
delivered into this pin exceeds 70 A, a low logic level (disable)
is generated at the output of the feedback circuit. This output
is sampled at the beginning of each cycle on the rising edge of
the clock signal. If high, the power MOSFET is turned on for
that cycle (enabled), otherwise the power MOSFET remains
off (disabled). Since the sampling is done only at the beginning
of each cycle, subsequent changes in the FB pin voltage or
current during the remainder of the cycle are ignored. When
the FB pin voltage falls below 1.69 V, the oscillator frequency
linearly reduces to typically 48% at the auto-restart threshold
voltage of 0.8 V. This function limits the power supply output
current at output voltages below the rated voltage regulation
threshold V
R
(see Figure 1).
5.8 V Regulator and 6.3 V Shunt Voltage Clamp
The 5.8 V regulator charges the bypass capacitor connected to
the BYPASS pin to 5.8 V by drawing a current from the voltage
on the DRAIN, whenever the MOSFET is off. The BYPASS
pin is the internal supply voltage node. When the MOSFET
is on, the device runs off of the energy stored in the bypass
capacitor. Extremely low power consumption of the internal
circuitry allows LinkSwitch-LP to operate continuously from the
current drawn from the DRAIN pin. A bypass capacitor value of
0.1 F is suffi cient for both high frequency decoupling and
energy storage.
In addition, there is a 6.3 V shunt regulator clamping the
BYPASS pin at 6.3 V when current is provided to the BYPASS
pin externally. This facilitates powering the device externally
through a resistor from the bias winding to decrease the no-
load consumption.
BYPASS Pin Under-Voltage
The BYPASS pin under-voltage circuitry disables the power
MOSFET when the BYPASS pin voltage drops below 4.85 V.
Once the BYPASS pin voltage drops below 4.85 V, it must rise
back to 5.8 V to enable (turn-on) the power MOSFET.
Over-Temperature Protection
The thermal shutdown circuitry senses the die temperature.
The threshold is set at 142 C typical with a 75 C hysteresis.
When the die temperature rises above this threshold (142 C)
the power MOSFET is disabled and remains disabled until the
die temperature falls by 75 C, at which point the MOSFET
is re-enabled.
Current Limit
The current limit circuit senses the current in the power MOSFET.
When this current exceeds the internal threshold (I
LIMIT
), the
power MOSFET is turned off for the remainder of that cycle. The
leading edge blanking circuit inhibits the current limit comparator
for a short time (t
LEB
) after the power MOSFET is turned on. This
leading edge blanking time has been set so that current spikes
caused by capacitance and rectifi er reverse recovery time will
not cause premature termination of the MOSFET conduction.
Auto Restart
In the event of a fault condition such as output short circuit or
an open loop condition, LinkSwitch-LP enters into auto-restart
operation. An internal counter clocked by the oscillator gets reset
every time the FB pin voltage exceeds the FEEDBACK Pin
Auto-Restart Threshold Voltage (V
FB(AR)
). If the FB pin voltage
drops below V
FB(AR)
for more than 100 ms, the power MOSFET
switching is disabled. The auto-restart alternately enables and
disables the switching of the power MOSFET at a duty cycle
of typically 12% until the fault condition is removed.
Figure 4. Frequency Jitter at f
OSC
.
600
0
20
68 kHz
64 kHz
V
DRAIN
Time (
s)
PI-
3
660-0
8
1
3
0
3
500
400
300
200
100
0
4
LNK562-564
F
10/05
Applications Example
The circuit shown in Figure 5 is a typical implementation of
a 6 V, 330 mA, constant voltage, constant current (CV/CC)
output power supply.
AC input differential fi ltering is accomplished with the very
low cost input fi lter stage formed by C1 and L1. The proprietary
frequency jitter feature of the LNK564 eliminates the need for
an input pi fi lter, so only a single bulk capacitor is required.
Adding a sleeve may allow the input inductor L1 to be used as a
fuse as well as a fi lter component. This very simple FilterfuseTM
input stage further reduces system cost. Alternatively, a fusible
resistor RF1 may be used to provide the fusing function.
Input diode D2 may be removed from the neutral phase in
applications where decreased EMI margins and/or decreased
input surge withstand is allowed. In such applications, D1 will
need to be an 800 V diode.
The power supply utilizes simplifi ed bias winding voltage
feedback, enabled by LNK564 ON/OFF control. The resistor
divider formed by R1 and R2 determine the output voltage across
the transformer bias winding during the switch OFF time. In the
V/I constant voltage region, the LNK564 device enables/disables
switching cycles to maintain 1.69 V on the FB pin. Diode D3 and
low cost ceramic capacitor C3 provide rectifi cation and fi ltering
of the primary feedback winding waveform. At increased loads,
beyond the constant power threshold, the FB pin voltage begins
to reduce as the power supply output voltage falls. The internal
oscillator frequency is linearly reduced in this region until it
reaches typically 50% of the starting frequency. When the FB
pin voltage drops below the auto-restart threshold (typically
0.8 V on the FB pin, which is equivalent to 1 V to 1.5 V at the
output of the power supply), the power supply will turn OFF
for 800 ms and then turn back on for 100 ms. It will continue
in this mode until the auto-restart threshold is exceeded. This
function reduces the average output current during an output
short circuit condition.
No-load consumption can be further reduced by increasing C3
to 0.47 F or higher.
A Clampless primary circuit is achieved due to the very
tight tolerance current limit trimming techniques used in
manufacturing the LNK564, plus the transformer construction
techniques used. Peak drain voltage is therefore limited to
typically less than 550 V at 265 VAC, providing signifi cant
margin to the 700 V minimum drain voltage specifi cation
(BV
DSS
).
Output rectifi cation and fi ltering is achieved with output rectifi er
D4 and fi lter capacitor C5. Due to the auto-restart feature, the
average short circuit output current is signifi cantly less than
1 A, allowing low cost rectifi er D4 to be used. Output circuitry is
designed to handle a continuous short circuit on the power supply
output. Diode D4 is an ultra-fast type, selected for optimum
V/I output characteristics. Optional resistor R3 provides a pre-
load, limiting the output voltage level under no-load output
conditions. Despite this pre-load, no-load consumption is within
targets at approximately 140 mW at 265 VAC. The additional
margin of no-load consumption requirement can be achieved
by increasing the value of R4 to 2.2 k or higher while still
maintaining output voltage well below the 9 V maximum
specifi cation. Placement is left on the board for an optional
Zener clamp (VR1) to limit maximum output voltage under
open loop conditions, if required.
Figure 5. 6 V, 330 mA CV/CC Linear Replacement Power Supply.
D
S
FB
BP
J3-1
RTN
6 V,
0.33 A
J3-2
L
J-1
J-2
N
D1
1N4937
RF1*
8.2
2.5 W
C1
10
F
400 V
C2
0.1
F
50 V
L1
3300
H
D4
UF4002
D3
1N4005
C5
220
F
25 V
C3
330 nF
50 V
C4*
100 pF
250 VAC
*Optional components
R3
2 k
VR1*
1N5240B
10 V
R2
3 k
R1
37.4 k
T1
EE16
2
1
7
6
4
5
D2
1N4005
90-265
VAC
LinkSwitch-LP
PI-4106-101105
U1
LNK564P
5
LNK562-564
F
10/05
Key Application Considerations
Output Power Table
The data sheet maximum output power table (Table 1) represents
the maximum practical continuous output power level that can
be obtained under the following assumed conditions:
1. The minimum DC input voltage is 90 V or higher for 85 VAC
input, or 240 V or higher for 230 VAC input or 115 VAC
with a voltage doubler. The value of the input capacitance
should be large enough to meet these criteria for AC input
designs.
2. Secondary output of 6 V with a Schottky rectifi er diode.
3. Assumed effi ciency of 70%.
4. Voltage only output (no secondary-side constant current
circuit).
5. Discontinuous mode operation (K
P
> 1).
6. A suitably sized core to allow a practical transformer design
(see Table 2).
7. The part is board mounted with SOURCE pins soldered
to a suffi cient area of copper to keep the SOURCE pin
temperature at or below 100 C.
8. Ambient temperature of 50 C for open frame designs
and an internal enclosure temperature of 60 C for adapter
designs.
Below a value of 1, K
P
is the ratio of ripple to peak primary
current. Above a value of 1, K
P
is the ratio of primary MOSFET
OFF time to the secondary diode conduction time. Due to
the fl ux density requirements described below, typically a
LinkSwitch-LP design will be discontinuous, which also has
the benefi t of allowing lower-cost fast (vs. ultra-fast) output
diodes and reducing EMI.
Clampless Designs
Clampless designs rely solely on the drain node capacitance
to limit the leakage inductance induced peak drain-to-source
voltage. Therefore the maximum AC input line voltage, the
value of V
OR
, the leakage inductance energy, (a function of
leakage inductance and peak primary current), and the primary
winding capacitance determine the peak drain voltage. With no
signifi cant dissipative element present, as is the case with an
external clamp, the longer duration of the leakage inductance
ringing can increase EMI.
The following requirements are recommended for a universal
input or 230 VAC only Clampless design:
1. Clampless designs should only be used for P
O
2.5 W using
a V
OR
of 90 V
2. For designs with P
O
2 W, a two-layer primary must be
used to ensure adequate primary intra-winding capacitance
in the range of 25 pF to 50 pF.
3. For designs with 2 < P
O
2.5 W, a bias winding must be added
to the transformer using a standard recovery rectifi er diode
(1N4003 1N4007) to act as a clamp. This bias winding may
also be used to externally power the device by connecting
a resistor from the bias winding capacitor to the BYPASS
pin. This inhibits the internal high voltage current source,
reducing device dissipation and no-load consumption.
4. For designs with P
O
> 2.5 W, Clampless designs are not
practical and an external RCD or Zener clamp should be
used.
5. Ensure that worst-case, high line, peak drain voltage is below
the BV
DSS
specifi cation of the internal MOSFET and ideally
650 V to allow margin for design variation.
V
OR
(Refl ected Output Voltage), is the secondary output plus
output diode forward voltage drop that is refl ected to the
primary via the turns ratio of the transformer during the diode
conduction time. The V
OR
adds to the DC bus voltage and the
leakage spike to determine the peak drain voltage.
Audible Noise
The cycle skipping mode of operation used in LinkSwitch-LP
can generate audio frequency components in the transformer.
To limit this audible noise generation, the transformer should
be designed such that the peak core fl ux density is below
1500 Gauss (150 mT). Following this guideline and using the
standard transformer production technique of dip varnishing,
practically eliminates audible noise. Vacuum impregnation
of the transformer is not recommended, as it does not provide
any better reduction of audible noise than dip varnishing. And
although vacuum impregnation has the benefi t of increased
transformer capacitance (which helps in Clampless designs),
it can also upset the mechanical design of the transformer,
especially if shield windings are used. Higher fl ux densities are
possible, increasing the power capability of the transformers
above what is shown in Table 2. However careful evaluation of
the audible noise performance should be made using production
transformer samples before approving the design.
Ceramic capacitors that use dielectrics such as Z5U, when used
in clamp circuits, may also generate audio noise. If this is the
case, try replacing them with a capacitor having a different
dielectric or construction, for example a fi lm type.
Bias Winding Feedback
To give the best output regulation in bias winding designs, a
slow diode such as the 1N400x series should be used as the
LinkSwitch-LP
Device
Core Size
LNK562
LNK563
LNK564
EE13
1.1 W
1.4 W
1.7 W
EE16
1.3 W
1.7 W
2 W
EE19
1.9 W
2.5 W
3 W
Table 2. Estimate of Transformer Power Capability vs.
LinkSwitch-LP Device and Core Size at a Flux Density of
1500 Gauss (150 mT).
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