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Datasheet: I74F50728N (Philips Semiconductors)

Synchronizing cascaded dual positive edge-triggered D-type flip-flop

 

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Philips Semiconductors
Philips
Semiconductors
74F50728
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
Positive specification
IC15 Data Handbook
1990 Sep 14
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74F50728
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
2
September 14, 1990
853-1389 00421
FEATURES
Metastable immune characteristics
Output skew less than 1.5ns
See 74F5074 for synchronizing dual D-type flip-flop
See 74F50109 for synchronizing dual JK positive edge-triggered
flip-flop
See 74F50729 for synchronizing dual dual D-type flip-flop with
edge-triggered set and reset
Industrial temperature range available (40
C to +85
C)
DESCRIPTION
The 74F50728 is a cascaded dual positive edgetriggered Dtype
featuring individual data, clock, set and reset inputs; also true and
complementary outputs.
Set (SDn) and reset (RDn) are asynchronous active low inputs and
operate independently of the clock (CPn) input. They set and reset
both flipflops of a cascaded pair simultaneously. Data must be
stable just one setup time prior to the lowtohigh transition of the
clock for guaranteed propagation delays.
Clock triggering occurs at a voltage level and is not directly related
to the transition time of the positivegoing pulse. Following the hold
time interval, data at the Dn input may be changed without affecting
the levels of the output. Data entering the 74F50728 requires two
clock cycles to arrive at the outputs.
The 74F50728 is designed so that the outputs can never display a
metastable state due to setup and hold time violations. If setup time
and hold time are violated the propagation delays may be extended
beyond the specifications but the outputs will not glitch or display a
metastable state. Typical metastability parameters for the 74F50728
are:
135
ps and
T
0
9.8 X 10
6
sec where
represents a
function of the rate at which a latch in a metastable state resolves
that condition and T
o
represents a function of the measurement of
the propensity of a latch to enter a metastable state.
TYPE
TYPICAL f
max
TYPICAL SUPPLY
CURRENT (TOTAL)
74F50728
145 MHz
23mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
INDUSTRIAL RANGE
DESCRIPTION
V
CC
= 5V
10%,
V
CC
= 5V
10%,
PKG DWG #
T
amb
= 0
C to +70
C
T
amb
= 40
C to +85
C
14pin plastic DIP
N74F50728N
I74F50728N
SOT27-1
14pin plastic SO
N74F50728D
I74F50728D
SOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/
LOW
LOAD VALUE HIGH/
LOW
D0, D1
Data inputs
1.0/0.417
20
A/250
A
CP0, CP1
Clock inputs (active rising edge)
1.0/1.0
20
A/20
A
SD0, SD1
Set inputs (active low)
1.0/1.0
20
A/20
A
RD0, RD1
Reset inputs (active low)
1.0/1.0
20
A/20
A
Q0, Q1, Q0, Q1
Data outputs
50/33
1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20
A in the high state and 0.6mA in the low state.
Philips Semiconductors
Product specification
74F50728
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
September 14, 1990
3
PIN CONFIGURATION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
V
CC
SD1
Q1
Q1
CP1
RD1
D1
RD0
D0
Q0
CP0
SD0
Q0
SF00605
LOGIC SYMBOL
D1
D0
Q0 Q0 Q1 Q1
5
6
9
8
2
12
V
CC
= Pin 14
GND = Pin 7
CP0
SD0
RD0
CP1
SD1
RD1
3
4
1
11
10
13
SF00606
IEC/IEEE SYMBOL
3
6
9
8
&
S
C1
1D
R
S
C2
2D
R
SF00607
4
3
2
1
10
11
12
13
LOGIC DIAGRAM
D
Q
Q
CP
D
Q
Q
CP
Qn
Q n
CPn
5, 9
6, 8
4, 10
2, 12
3, 11
1, 13
Vcc = Pin 14
GND = Pin 7
SDn
SF00608
Dn
RDn
NOTE: Data entering the flipflop requires two clock cycles to
arrive at the output.
SYNCHRONIZING SOLUTIONS
Synchronizing incoming signals to a system clock has proven to be
costly, either in terms of time delays or hardware. The reason for this
is that in order to synchronize the signals a flipflop must be used to
"capture" the incoming signal. While this is perhaps the only way to
synchronize a signal, to this point, there have been problems with
this method. Whenever the flop's setup or hold times are violated
the flop can enter a metastable state causing the outputs in turn to
glitch, oscillate, enter an intermediate state or change state in some
abnormal fashion. Any of these conditions could be responsible for
causing a system crash. To minimize this risk, flipflops are often
cascaded so that the input signal is captured on the first clock pulse
and released on the second clock pulse (see Fig.1). This gives the
first flop about one clock period minus the flop delay and minus the
second flop's clocktoQ setup time to resolve any metastable
condition. This method greatly reduces the probability of the outputs
of the synchronizing device displaying an abnormal state but the
trade-off is that one clock cycle is lost to synchronize the incoming
data and two separate flipflops are required to produce the
cascaded flop circuit. In order to assist the designer of synchronizing
circuits Philips Semiconductors is offering the 74F50728.
D
Q
Q
CP
D
Q
Q
CP
Q OUTPUT
Q OUTPUT
DATA
CLOCK
SF00609
Figure 1.
The 50728 consists of two pair of cascaded Dtype flipflops with
metastable immune features and is pin compatible with the 74F74.
Because the flops are cascaded on a single part the metastability
Philips Semiconductors
Product specification
74F50728
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
September 14, 1990
4
characteristics are greatly improved over using two separate flops
that are cascaded. The pin compatibility with the 74F74 allows for
plugin retrofitting of previously designed systems.
Because the probability of failure of the 74F50728 is so remote, the
metastability characteristics of the part were empirically determined
based on the characteristics of its sister part, the 74F5074. The
table below shows the 74F5074 metastability characteristics.
Having determined the T
0
and
of the flop, calculating the mean
time between failures (MTBF) for the 74F50728 is simple. It is,
however, somewhat different than calculating MTBF for a typical part
because data requires two clock pulses to transit from the input to
the output. Also, in this case a failure is considered of the output
beyond the normal propagation delay.
Suppose a designer wants to use the flop for synchronizing
asynchronous data that is arriving at 10MHz (as measured by a
frequency counter), and is using a clock frequency of 50MHz. He
simply plugs his number into the equation below:
MTBF = e
(t'/t)
/T
o
f
C
f
I
In this formula, f
C
is the frequency of the clock, f
I
is the average
input event frequency, and t' is the period of the clock input (20
nanoseconds). In this situation the f
I
will be twice the data
frequency of 20 MHz because input events consist of both of low
and high data transitions. From Fig. 2 it is clear that the MTBF is
greater than 10
41
seconds. Using the above formula the actual
MTBF is 2.23 X 10
42
seconds or about 7 X 10
34
years.
TYPICAL VALUES FOR
AND T
0
AT VARIOUS V
CC
S AND TEMPERATURES
T
amb
= 0
C
T
amb
= 25
C
T
amb
= 70
C
T
0
T
0
T
0
V
CC
= 5.5V
125ps
1.0 X 10
9
sec
138ps
5.4 X 10
6
sec
160ps
1.7 X 10
5
sec
V
CC
= 5.0V
115ps
1.3 X 10
10
sec
135ps
9.8 X 10
6
sec
167ps
3.9 X 10
4
sec
V
CC
= 4.5V
115ps
3.4 X 10
13
sec
132ps
5.1 X 10
8
sec
175ps
7.3 X 10
4
sec
MEAN TIME BETWEEN FAILURES VERSUS DATA FREQUENCY AT VARIOUS CLOCK FREQUENCY
10
70
10
60
10
50
10
40
10
30
10
20
10
10
10
00
1K
100K
10M
Data frequency (Hz)
Mean time
between failures
(seconds)
Clock = 40MHz
Clock = 50MHz
Clock = 650MHz
Clock = 70MHz
Clock = 80MHz
Clock = 100MHz
1 billion years
NOTE: V
CC
= 5V, T
amb
= 25
C,
=135ps, To = 9.8 X 10
8
sec
SF00610
Figure 2.
Philips Semiconductors
Product specification
74F50728
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
September 14, 1990
5
FUNCTION TABLE
INTERNAL
OUTPUTS
INPUTS
REGISTER
OUTPUTS
OPERATING MODE
SDn
RDn
CPn
Dn
Q
Qn
Qn
L
H
X
X
H
H
L
Asynchronous set
H
L
X
X
L
L
H
Asynchronous reset
L
L
X
X
X
H
H
Undetermined*
H
H
h
h
H
L
Load "1"
H
H
l
l
L
H
Load "0"
H
H
L
X
NC
NC
NC
Hold
NOTES:
H = High voltage level
h = High voltage level one setup time prior to lowtohigh
clock transition
L
= Low voltage level
l
= Low voltage level one setup time prior to lowtohigh
clock transition
NC= No change from the previous setup
X = Don't care
*
= This setup is unstable and will change when either set of
reset return to the highlevel
= Lowtohigh clock transition.
** = Data entering the flipflop requires two clock cycles to
arrive at the output (see logic diagram)
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
CC
Supply voltage
0.5 to +7.0
V
V
IN
Input voltage
0.5 to +7.0
V
I
IN
Input current
30 to +5
mA
V
OUT
Voltage applied to output in high output state
0.5 to V
CC
V
I
OUT
Current applied to output in low output state
40
mA
T
amb
Operating free air temperature range
Commercial range
0 to +70
C
Industrial range
40 to +85
C
T
stg
Storage temperature range
65 to +150
C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
MIN
NOM
MAX
UNIT
V
CC
Supply voltage
4.5
5.0
5.5
V
V
IH
Highlevel input voltage
2.4
V
V
IL
Lowlevel input voltage
0.8
V
I
Ik
Input clamp current
18
mA
I
OH
Highlevel output current
3
mA
I
OL
Lowlevel output current
20
mA
T
amb
Operating free air temperature range
Commercial range
0
+70
C
Industrial range
40
+85
C
Philips Semiconductors
Product specification
74F50728
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
September 14, 1990
6
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
CONDITIONS
1
MIN
TYP
2
MAX
V
OH
High-level output voltage
V
CC
= MIN, V
IH
= MIN
I
OH
= MAX
10%V
CC
2.5
V
V
IL
= MAX,
5%V
CC
2.7
3.4
V
V
OL
Low-level output voltage
V
CC
= MIN, V
IL
=
MAX,
I
OL
= MAX
10%V
CC
0.30
0.50
V
V
IH
= MIN
5%V
CC
0.30
0.50
V
V
IK
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
-0.73
-1.2
V
I
I
Input current at maximum input voltage
V
CC
= MAX, V
I
= 7.0V
100
A
I
IH
Highlevel input current
V
CC
= MAX, V
I
= 2.7V
20
A
I
IL
Lowlevel input current
Dn
V
CC
= MAX, V
I
= 0.5V
-250
A
CPn, SDn, RDn
20
A
I
OS
Shortcircuit output current
3
V
CC
= MAX, V
O
= 2.25V
-60
-150
mA
I
CC
Supply current
4
(total)
V
CC
= MAX
23
34
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
4. Measure I
CC
with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
amb
= +25
C
T
amb
= 0
C to
+70
C
T
amb
= 40
C to +85
C
SYMBOL
PARAMETER
TEST
V
CC
= +5.0V
V
CC
= +5.0V
10%
V
CC
= +5.0V
10%
UNIT
CONDITION
C
L
= 50pF,
R
L
= 500
C
L
= 50pF,
R
L
= 500
C
L
= 50pF,
R
L
= 500
MIN
TYP
MAX
MIN
MAX
MIN
MAX
f
max
Maximum clock frequency
Waveform 1
100
145
85
70
ns
t
PLH
t
PHL
Propagation delay
CPn to Qn or Qn
Waveform 1
2.0
2.0
3.8
3.8
6.0
6.0
1.5
2.0
6.5
6.5
1.5
2.0
7.5
7.0
ns
t
PLH
t
PHL
Propagation delay
SDn RDn
to Qn or Qn
Waveform 2
3.5
3.5
5.0
5.0
8.0
8.0
3.0
3.0
9.0
8.5
3.0
3.0
10.5
10.0
ns
t
sk(o)
Output skew
1, 2
Waveform 4
1.5
1.5
1.5
ns
NOTES TO AC ELECTRICAL CHARACTERISTICS
1. | t
PLH
actual t
PHL
actual | for any one output compare to any other output where N and M are either LH or HL.
2. Skew lines are valid only under same conditions (temperature, V
CC
, loading, etc.,).
Philips Semiconductors
Product specification
74F50728
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
September 14, 1990
7
AC SETUP REQUIREMENTS
LIMITS
T
amb
= +25
C
T
amb
= 0
C to
+70
C
T
amb
= 40
C to +85
C
SYMBOL
PARAMETER
TEST
V
CC
= +5.0V
V
CC
= +5.0V
10%
V
CC
= +5.0V
10%
UNIT
CONDITION
C
L
= 50pF,
R
L
= 500
C
L
= 50pF,
R
L
= 500
C
L
= 50pF,
R
L
= 500
MIN
TYP
MAX
MIN
MAX
MIN
MAX
t
su
(H)
t
su
(L)
Setup time, high or low
Dn to CPn
Waveform 1
1.5
1.5
2.0
2.0
2.0
2.0
ns
t
h
(H)
t
h
(L)
Hold time, high or low
Dn to CPn
Waveform 1
0.0
0.0
1.5
1.5
1.5
1.5
ns
t
w
(H)
t
w
(L)
CPn pulse width,
high or low
Waveform 2
3.0
4.0
3.5
5.0
4.0
5.5
ns
t
w
(L)
SDn, RDn pulse width, low
Waveform 2
4.5
4.0
4.5
ns
t
rec
Recovery time
SDn, RDn to CPn
Waveform 3
3.5
3.5
3.5
ns
AC WAVEFORMS
VM
VM
CPn
VM
VM
VM
VM
VM
VM
tsu(H)
th(H)
Jn, Kn
Qn
VM
tw(H)
1/fmax
tsu(L)
th(L)
VM
VM
tPLH
Qn
tw(L)
tPHL
tPHL
tPLH
SF00139
Waveform 1. Propagation delay for data to output, data setup
time and hold times, and clock width, and
maximum clock frequency
SDn or RDn
V
M
V
M
t
rec
CPn
SF00603
Waveform 3. Recovery time for set or reset to output
VM
VM
RDn
VM
Qn
VM
VM
VM
tPLH
Qn
tw(L)
tPHL
tPHL
tPLH
SDn
VM
VM
tw(L)
SF00050
Waveform 2. Propagation delay for set and reset to output,
set and reset pulse width
Qn, Qn
VM
VM
tsk(o)
Qn, Qn
SF00590
Waveform 4. Output skew
NOTES:
For all waveforms, V
M
= 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Philips Semiconductors
Product specification
74F50728
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
September 14, 1990
8
TEST CIRCUIT AND WAVEFORMS
tw
90%
VM
10%
90%
VM
10%
90%
VM
10%
90%
VM
10%
NEGATIVE
PULSE
POSITIVE
PULSE
tw
AMP (V)
0V
0V
tTHL (tf
)
INPUT PULSE REQUIREMENTS
rep. rate
t
w
t
TLH
t
THL
1MHz
500ns
2.5ns
2.5ns
Input Pulse Definition
VCC
family
74F
D.U.T.
PULSE
GENERATOR
RL
CL
RT
VIN
VOUT
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
R
L
= Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
C
L
= Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
R
T
= Termination resistance should be equal to Z
OUT
of
pulse generators.
tTHL (tf
)
tTLH (tr
)
tTLH (tr
)
AMP (V)
amplitude
3.0V
1.5V
V
M
SF00006
Philips Semiconductors
Product specification
74F50728
Synchronizing cascaded dual positive edge-triggered
D-type flip-flop
1990 Sep 14
9
DIP14:
plastic dual in-line package; 14 leads (300 mil)
SOT27-1
Philips Semiconductors
Product specification
74F50728
Synchronizing cascaded dual positive edge-triggered
D-type flip-flop
1990 Sep 14
10
SO14:
plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
Philips Semiconductors
Product specification
74F50728
Synchronizing cascaded dual positive edge-triggered
D-type flip-flop
1990 Sep 14
11
NOTES
Philips Semiconductors
Product specification
74F50728
Synchronizing cascaded dual positive edge-triggered
D-type flip-flop
yyyy mmm dd
12
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code
Date of release: 10-98
Document order number:
9397-750-05215
Philips
Semiconductors
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
[1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1]
Please consult the most recently issued datasheet before initiating or completing a design.
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