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Datasheet: I74F112N (Philips Semiconductors)

Dual J-K negative edge-triggered flip-flop

 

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Philips Semiconductors
Philips
Semiconductors
74F112
Dual J-K negative edge-triggered flip-flop
Product specification
IC15 Data Handbook
1990 Feb 09
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74F112
Dual J-K negative edge-triggered flip-flop
2
February 9, 1990
8530338 98775
FEATURE
Industrial temperature range available (40
C to +85
C)
DESCRIPTION
The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop,
feature individual J, K, Clock (CPn), Set (SD) and Reset (RD)
inputs, true (Qn) and complementary (Qn) outputs.
The SD and RD inputs, when Low, set or reset the outputs as shown
in the Function Table, regardless of the level at the other inputs.
A High level on the clock (CPn) input enables the J and K inputs and
data will be accepted. The logic levels at the J and K inputs may be
allowed to change while the CPn is High and flip-flop will perform
according to the Function Table as long as minimum setup and hold
times are observed. Output changes are initiated by the High-to-Low
transition of the CPn.
PIN CONFIGURATION
16
15
14
13
12
11
10
7
6
5
4
3
2
1
Q1
V
CC
K1
J1
SD1
CP1
RD0
RD1
CP0
K0
Q0
J0
SD0
Q0
9
8
GND
Q1
SF00103
TYPE
TYPICAL PROPAGATION DELAY
TYPICAL SUPPLY CURRENT (TOTAL)
74F112
100MHz
15mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
10%, T
amb
= 0
C to +70
C
INDUSTRIAL RANGE
V
CC
= 5V
10%, T
amb
= 40
C to +85
C
PKG DWG #
16-pin plastic DIP
N74F112N
I74F112N
SOT38-4
16-pin plastic SO
N74F112D
I74F112D
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
J0, J1
J inputs
1.0/1.0
20
A/0.6mA
K0, K1
K inputs
1.0/1.0
20
A/0.6mA
SD0, SD1
Set inputs (active Low)
1.0/5.0
20
A/3.0mA
RD0, RD1
Reset inputs (active Low)
1.0/5.0
20
A/3.0mA
CP0, CP1
Clock Pulse input (active falling edge)
1.0/4.0
20
A/2.4mA
Q0, Q0; Q1, Q1
Data outputs
50/33
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20
A in the High state and 0.6mA in the Low state.
Philips Semiconductors
Product specification
74F112
Dual J-K negative edge-triggered flip-flop
February 9, 1990
3
LOGIC SYMBOL
Q0 Q0 Q1 Q1
5
6
9
7
V
CC
= Pin 16
GND = Pin 8
1
4
15
13
10
14
CP0
SD0
RD0
CP1
SD1
RD1
J1
K0
2 12
SF00104
K1
J0
3
11
IEC/IEEE SYMBOL
SF00105
6
3
1
2
15
4
11
13
12
14
10
5
9
7
1J
C1
1K
R
S
2J
C2
2K
R
S
LOGIC DIAGRAM
5, 9
4, 10
2, 12
1, 13
6, 7
15, 14
3, 11
Qn
SDn
Kn
Qn
RDn
Jn
CPn
SF00106
V
CC
= Pin 16
GND = Pin 8
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
SD
RD
CP
J
K
Q
Q
OPERATING MODE
L
H
X
X
X
H
L
Asynchronous Set
H
L
X
X
X
L
H
Asynchronous Reset
L
L
X
X
X
H*
H*
Undetermined *
H
H
h
h
q
q
Toggle
H
H
l
h
L
H
Load "0" (Reset)
H
H
h
l
H
L
Load "1" (Set)
H
H
l
l
q
q
Hold "no change"
H
H
H
X
X
Q
Q
Hold "no change"
H = High voltage level
h = High voltage level one setup time prior to High-to-Low clock transition
L = Low voltage level
l = Low voltage level one setup time prior to High-to-Low clock transition
q = Lower case letters indicate the state of the reference output prior to the High-to-Low clock transition
X = Don't care
= High-to-Low clock transition
* = Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously.
Philips Semiconductors
Product specification
74F112
Dual J-K negative edge-triggered flip-flop
February 9, 1990
4
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
CC
Supply voltage
0.5 to +7.0
V
V
IN
Input voltage
0.5 to +7.0
V
I
IN
Input current
30 to +5
mA
V
OUT
Voltage applied to output in High output state
0.5 to V
CC
V
I
OUT
Current applied to output in Low output state
40
mA
T
Operating free air temperature range
Commercial range
0 to +70
C
T
amb
Operating free-air temperature range
Industrial range
40 to +85
C
T
stg
Storage temperature range
65 to +150
C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
NOM
MAX
UNIT
V
CC
Supply voltage
4.5
5.0
5.5
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level input voltage
0.8
V
I
IK
Input clamp current
18
mA
I
OH
High-level output current
1
mA
I
OL
Low-level output current
20
mA
T
Operating free air temperature range
Commercial range
0
+70
C
T
amb
Operating free-air temperature range
Industrial range
40
+85
C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
1
MIN
TYP
2
MAX
UNIT
V
O
High level output voltage
V
CC
= MIN, V
IL
= MAX
10%V
CC
2.5
V
V
OH
High-level output voltage
V
IH
= MIN, I
OH
= MAX
5%V
CC
2.7
3.4
V
V
O
Low level output voltage
V
CC
= MIN, V
IL
= MAX
10%V
CC
0.35
0.50
V
V
OL
Low-level output voltage
V
IH
= MIN, I
OL
= MAX
5%V
CC
0.35
0.50
V
V
IK
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
0.73
1.2
V
I
I
Input current at maximum input voltage
V
CC
= MAX, V
I
= 7.0V
100
A
I
IH
High-level input current
V
CC
= MAX, V
I
= 2.7V
20
A
Jn, Kn
0.6
mA
I
IL
Low-level input current
CPn
V
CC
= MAX, V
I
= 0.5V
2.4
mA
SDn, RDn
3.0
mA
I
OS
Short-circuit output current
3
V
CC
= MAX
60
150
mA
I
CC
Supply current (total)
4
V
CC
= MAX
15
21
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
4. Measure I
CC
with the clock input grounded and all outputs open, with the Q and Q outputs High in turn.
Philips Semiconductors
Product specification
74F112
Dual J-K negative edge-triggered flip-flop
February 9, 1990
5
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5.0V
T
amb
= +25
C
C
L
= 50pF
R
L
= 500
V
CC
= +5.0V
10%
T
amb
= 0
C to +70
C
C
L
= 50pF
R
L
= 500
V
CC
= +5.0V
10%
T
amb
= 40
C to +85
C
C
L
= 50pF
R
L
= 500
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
f
MAX
Maximum clock frequency
Waveform 1
85
100
80
80
MHz
t
PLH
t
PHL
Propagation delay
CP to Qn or Qn
Waveform 1
2.0
2.0
5.0
5.0
6.5
6.5
2.0
2.0
7.5
7.5
2.0
2.0
7.5
7.5
ns
t
PLH
t
PHL
Propagation delay
SDn, RD to Qn or Qn
Waveform 2,3
2.0
2.0
4.5
4.5
6.5
6.5
2.0
2.0
7.5
7.5
1.5
1.5
7.5
7.5
ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5.0V
T
amb
= +25
C
C
L
= 50pF
R
L
= 500
V
CC
= +5.0V
10%
T
amb
= 0
C to +70
C
C
L
= 50pF
R
L
= 500
V
CC
= +5.0V
10%
T
amb
= 40
C to +85
C
C
L
= 50pF
R
L
= 500
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
t
S
(H)
t
S
((L)
Setup time, High or Low
Jn, Kn to CP
Waveform 1
4.0
3.5
5.0
4.0
5.0
4.0
ns
t
h
(H)
t
h
(L)
Hold time, High or Low
Jn, Kn to CP
Waveform 1
0.0
0.0
0.0
0.0
0.0
0.0
ns
t
W
(H)
t
W
(L)
CP Pulse width
High or Low
Waveform 1
4.5
4.5
5.0
5.0
5.0
5.0
ns
t
W
(L)
SDn, RD Pulse width
Low
Waveform 2,3
4.5
5.0
5.0
ns
t
REC
Recovery time
SDn, RD to CP
Waveform 2,3
4.5
5.0
5.0
ns
AC WAVEFORMS
For all waveforms, V
M
= 1.5V.
VM
VM
CPn
VM
VM
VM
VM
VM
VM
ts(H)
th(H)
Jn, Kn
Qn
VM
tw(L)
fmax
ts(L)
th(L)
VM
VM
tPLH
Qn
tw(H)
tPHL
tPHL
tPLH
SF00107
The shaded areas indicate when the input is permitted to change for predictable output performance.
Waveform 1.
Propagation Delay for Data to Output, Data Setup Time and Hold Times, and Clock Pulse Width
Philips Semiconductors
Product specification
74F112
Dual J-K negative edge-triggered flip-flop
February 9, 1990
6
VM
CPn
Qn
VM
VM
Qn
tPHL
tPLH
SDn
VM
VM
tw(L)
SF00108
Jn, Kn
tREC
Waveform 2.
Propagation Delay for Set to Output, Set Pulse Width, and Recovery Time for Set to Clock
VM
CPn
Qn
VM
VM
Qn
tPLH
tPHL
RDn
VM
VM
tw(L)
SF00109
Jn, Kn
tREC
Waveform 3.
Propagation Delay for Reset to Output, Reset Pulse Width, and Recovery Time for Reset to Clock
Philips Semiconductors
Product specification
74F112
Dual J-K negative edge-triggered flip-flop
February 9, 1990
7
TEST CIRCUIT AND WAVEFORMS
tw
90%
VM
10%
90%
VM
10%
90%
VM
10%
90%
VM
10%
NEGATIVE
PULSE
POSITIVE
PULSE
tw
AMP (V)
0V
0V
tTHL (tf
)
INPUT PULSE REQUIREMENTS
rep. rate
t
w
t
TLH
t
THL
1MHz
500ns
2.5ns
2.5ns
Input Pulse Definition
VCC
family
74F
D.U.T.
PULSE
GENERATOR
RL
CL
RT
VIN
VOUT
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
R
L
= Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
C
L
= Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
R
T
= Termination resistance should be equal to Z
OUT
of
pulse generators.
tTHL (tf
)
tTLH (tr
)
tTLH (tr
)
AMP (V)
amplitude
3.0V
1.5V
V
M
SF00006
Philips Semiconductors
Product specification
74F112
Dual J-K negative edge-triggered flip-flop
1990 Feb 09
8
DIP16:
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
Philips Semiconductors
Product specification
74F112
Dual J-K negative edge-triggered flip-flop
1990 Feb 09
9
SO16:
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
Philips Semiconductors
Product specification
74F112
Dual J-K negative edge-triggered flip-flop
yyyy mmm dd
10
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code
Date of release: 10-98
Document order number:
9397-750-05071
Philips
Semiconductors
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
[1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1]
Please consult the most recently issued datasheet before initiating or completing a design.
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