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Datasheet: I74F109N (Philips Semiconductors)

Positive J-K positive edge-triggered flip-flops

 

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Philips Semiconductors
Philips
Semiconductors
74F109
Positive J-K positive edge-triggered
flip-flops
Product specification
IC15 Data Handbook
1990 Oct 23
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74F109
Postive J-K positive edge-triggered flip-flops
2
October 23, 1990
8530337 00783
FEATURE
Industrial temperature range available (40
C to +85
C)
DESCRIPTION
The 74F109 is a dual positive edge-triggered JK-type flip-flop
featuring individual J, K, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active low inputs and operate independently of the clock (CP) input.
The J and K are edge-triggered inputs which control the state
changes of the flip-flops as described in the function table. Clock
triggering occurs at a voltage level and is not directly related to the
transition time of the positive-going pulse. The J and K inputs must
be stable just one setup time prior to the low-to-high transition of the
clock for predictable operation. The JK design allows operation as a
D flip-flop by tying J and K inputs together. Although the clock input
is level sensitive, the positive transition of the clock pulse between
the 0.8V and 2.0V levels should be equal to or less than the clock to
output delay time for reliable operation.
PIN CONFIGURATION
16
15
14
13
12
11
10
7
6
5
4
3
2
1
Q0
V
CC
CP1
SD1
Q1
K1
RD1
J1
RD0
J0
Q0
K0
CP0
SD0
9
8
GND
Q1
SF00135
TYPE
TYPICAL f
max
TYPICAL SUPPLY CURRENT
(TOTAL)
74F109
125MHz
12.3mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
10%, T
amb
= 0
C to +70
C
INDUSTRIAL RANGE
V
CC
= 5V
10%, T
amb
= 40
C to +85
C
PKG DWG #
16-pin plastic DIP
N74F109N
I74F109N
SOT38-4
16-pin plastic SO
N74F109D
I74F109D
SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
J0, J1
J inputs
1.0/1.0
20
A/0.6mA
K0, K1
K inputs
1.0/1.0
20
A/0.6mA
CP0, CP1
Clock inputs (active rising edge)
1.0/1.0
20
A/0.6mA
SD0, SD1
Set inputs (active Low)
1.0/3.0
20
A/1.8mA
RD0, RD1
Reset inputs (active Low)
1.0/3.0
20
A/1.8mA
Q0, Q1, Q0, Q1
Data outputs
50/33
1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20
A in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
J1
J0
Q0 Q0 Q1 Q1
V
CC
= Pin 16
GND = Pin 8
K1
K0
2 14 3 13
6 7 10 9
CP0
SD0
RD0
CP1
SD1
RD1
4
5
1
12
11
15
SF00136
IEC/IEEE SYMBOL
SF00137
7
2
4
3
1
5
14
12
13
15
11
6
10
9
1J
C1
1K
R
S
2J
C2
2K
R
S
Philips Semiconductors
Product specification
74F109
Postive J-K positive edge-triggered flip-flops
October 23, 1990
3
LOGIC DIAGRAM
V
CC
= Pin 16
GND = Pin 8
K
Q
Q
CP
4, 12
3, 13
6, 10
7, 9
2, 14
5, 11
1, 15
SD
RD
J
SF00138
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
SD
RD
CP
J
K
Q
Q
OPERATING MODE
L
H
X
X
X
H
L
Asynchronous set
H
L
X
X
X
L
H
Asynchronous reset
L
L
X
X
X
H
H
Undetermined*
H
H
X
X
q
q
Hold
H
H
h
l
q
q
Toggle
H
H
h
h
H
L
Load "1" (set)
H
H
l
l
L
H
Load "0" (reset)
H
H
l
h
q
q
Hold 'no change"
NOTES:
H = High-voltage level
h
= High-voltage level one setup time prior to low-to-high
clock transition
L
= Low-voltage level
l
= Low-voltage level one setup time prior to low-to-high
clock transition
q
= Lower case indicate the state of the referenced output
prior to the low-to-high clock transition
X = Don't care
= Low-to-high clock transition
= Not low-to-high clock transition
*
= Both outputs will be high if both SD and RD go low
simultaneously
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
CC
Supply voltage
0.5 to +7.0
V
V
IN
Input voltage
0.5 to +7.0
V
I
IN
Input current
30 to +5
mA
V
OUT
Voltage applied to output in High output state
0.5 to V
CC
V
I
OUT
Current applied to output in Low output state
40
mA
T
Operating free air temperature range
Commercial range
0 to +70
C
T
amb
Operating free-air temperature range
Industrial range
40 to +85
C
T
stg
Storage temperature range
65 to +150
C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
NOM
MAX
UNIT
V
CC
Supply voltage
4.5
5.0
5.5
V
V
IN
High-level input voltage
2.0
V
V
IL
Low-level input voltage
0.8
V
I
IK
Input clamp current
18
mA
I
OH
High-level output current
1
mA
I
OL
Low-level output current
20
mA
T
Operating free air temperature range
Commercial range
0
+70
C
T
amb
Operating free-air temperature range
Industrial range
40
+85
C
Philips Semiconductors
Product specification
74F109
Postive J-K positive edge-triggered flip-flops
October 23, 1990
4
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
1
MIN
TYP
2
MAX
UNIT
V
O
High level output voltage
V
CC
= MIN, V
IL
= MAX,
I
O
= MAX
10%V
CC
2.5
V
V
OH
High-level output voltage
V
CC
MIN, V
IL
MAX,
V
IH
= MIN
I
OH
= MAX
5%V
CC
2.7
3.4
V
V
O
Low level output voltage
V
CC
= MIN, V
IL
= MAX,
I
OL
= MAX
10%V
CC
0.30
0.50
V
V
OL
Low-level output voltage
V
CC
MIN, V
IL
MAX,
V
IH
= MIN
5%V
CC
0.30
0.50
V
V
IK
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
0.73
1.2
V
I
I
Input current at maximum input voltage
V
CC
= MAX, V
I
= 7.0V
100
A
I
IH
High-level input current
V
CC
= MAX, V
I
= 2.7V
20
A
I
Low level input current
J, K, CPn
V
CC
= MAX, V
I
= 0.5V
0.6
mA
I
IL
Low-level input current
SDn, RDn
V
CC
= MAX, V
I
= 0.5V
1.8
mA
I
OS
Short-circuit output current
3
V
CC
= MAX
-60
150
mA
I
CC
Supply current
4
(total)
V
CC
= MAX
12.3
17
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
4. Measure I
CC
with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5.0V
T
amb
= +25
C
C
L
= 50pF
R
L
= 500
V
CC
= +5.0V
10%
T
amb
= 0
C to +70
C
C
L
= 50pF
R
L
= 500
V
CC
= +5.0V
10%
T
amb
= 40
C to +85
C
C
L
= 50pF
R
L
= 500
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
f
MAX
Maximum clock frequency
Waveform 1
90
125
90
90
MHz
t
PLH
t
PHL
Propagation delay
CPn to Qn or Qn
Waveform 1
3.8
4.4
5.3
6.2
7.0
8.0
3.8
4.4
8.0
9.2
3.8
4.4
9.0
9.2
ns
t
PLH
t
PHL
Propagation delay
SDn, RD to Qn or Qn
Waveform 2, 3
3.2
3.5
5.2
7.0
7.0
9.0
3.2
3.5
8.0
10.5
2.8
3.5
9.0
10.5
ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5.0V
T
amb
= +25
C
C
L
= 50pF
R
L
= 500
V
CC
= +5.0V
10%
T
amb
= 0
C to +70
C
C
L
= 50pF
R
L
= 500
V
CC
= +5.0V
10%
T
amb
= 40
C to +85
C
C
L
= 50pF
R
L
= 500
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
t
su
(H)
t
su
(L)
Setup time, high or low
Dn to CPn
Waveform 1
3.0
3.0
3.0
3.0
3.0
3.0
ns
t
h
(H)
t
h
(L)
Hold time, high or low
Dn to CPn
Waveform 1
1.0
1.0
1.0
1.0
1.0
1.0
ns
t
w
(H)
t
w
(L)
CP pulse width,
high or low
Waveform 1
4.0
5.0
4.0
5.0
4.0
5.0
ns
t
w
(L)
SDn or RDn pulse width,
low
Waveform 2
4.0
4.0
4.0
ns
t
rec
Recovery time
SDn or RDn to CP
Waveform 3
2.0
2.0
2.0
ns
Philips Semiconductors
Product specification
74F109
Postive J-K positive edge-triggered flip-flops
October 23, 1990
5
AC WAVEFORMS
For all waveforms, V
M
= 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VM
VM
CPn
VM
VM
VM
VM
VM
VM
tsu(H)
th(H)
Jn, Kn
Qn
VM
tw(H)
1/fmax
tsu(L)
th(L)
VM
VM
tPLH
Qn
tw(L)
tPHL
tPHL
tPLH
SF00139
Waveform 1. Propagation Delay for Data to Output, Data Setup
Time and Hold Times, and Clock Width,and Maximum
Clock Frequency
VM
VM
RDn
VM
Qn
VM
VM
VM
tPLH
Qn
tw(L)
tPHL
tPHL
tPLH
SDn
VM
VM
tw(L)
SF00050
Waveform 2. Propagation Delay for Set and Reset to Output,
Set and Reset Pulse Width
SDn or RDn
VM
VM
trec
CPn
SF00051
Waveform 3. Recovery Timer for Set or Reset to Clock
Philips Semiconductors
Product specification
74F109
Postive J-K positive edge-triggered flip-flops
October 23, 1990
6
TEST CIRCUIT AND WAVEFORMS
tw
90%
VM
10%
90%
VM
10%
90%
VM
10%
90%
VM
10%
NEGATIVE
PULSE
POSITIVE
PULSE
tw
AMP (V)
0V
0V
tTHL (tf
)
INPUT PULSE REQUIREMENTS
rep. rate
t
w
t
TLH
t
THL
1MHz
500ns
2.5ns
2.5ns
Input Pulse Definition
VCC
family
74F
D.U.T.
PULSE
GENERATOR
RL
CL
RT
VIN
VOUT
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
R
L
= Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
C
L
= Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
R
T
= Termination resistance should be equal to Z
OUT
of
pulse generators.
tTHL (tf
)
tTLH (tr
)
tTLH (tr
)
AMP (V)
amplitude
3.0V
1.5V
V
M
SF00006
Philips Semiconductors
Product specification
74F109
Positive J-K positive edge-triggered flip-flops
1990 Oct 23
7
DIP16:
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
Philips Semiconductors
Product specification
74F109
Positive J-K positive edge-triggered flip-flops
1990 Oct 23
8
SO16:
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
Philips Semiconductors
Product specification
74F109
Positive J-K positive edge-triggered flip-flops
1990 Oct 23
9
NOTES
Philips Semiconductors
Product specification
74F109
Positive J-K positive edge-triggered flip-flops
yyyy mmm dd
10
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code
Date of release: 10-98
Document order number:
9397-750-05069
Philips
Semiconductors
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
[1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1]
Please consult the most recently issued datasheet before initiating or completing a design.
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