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Datasheet: PI2EQX4401ZFE (Pericom Semiconductor Corporation)

2.5Gbps x1 Lane Serial PCI Express Repeater/Equalizer with Clock Buffer

 

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Pericom Semiconductor Corporation
1
PS8777B 02/15/06
Features
One high-speed PCI Express lane
Adjustable Transmiter De-Emphasis & Amplitude
Adjustable Receiver Equalization
One Spread Spectrum Reference Clock Buffer Output
100 Differential CML I/O's
Low Power (100mW per Channel)
Stand-by Mode Power Down State
V
CC
Operating Range: 1.8V 0.1V
Built in Clock Buffer
Packaging (Pb-free & Green):
-- 36-pad TQFN (ZF36)
Description
Pericom Semiconductor's PI2EQX4401 is a low power, PCI-
Express compliant signal re-driver. The device provides
programmable equalization, amplification, and de-emphasis
by using 4 select bits, SEL[0:3], to optimize performance
over a variety of physical mediums by reducing Inter-symbol
interference. PI2EQX4401 supports two 100 Differential CML
data I/O's between the Protocol ASIC to a switch fabric, across
a backplane, or extends the signals across other distant data
pathways on the user's platform.
The integrated equalization circuitry provides flexibility with
signal integrity of the PCI Express signal before the re-driver.
Whereas the integrated de-emphasis circuitry provides flexibility
with signal integrity of the PCI Express signal after the re-driver.
In addition to providing signal re-conditioning, Pericom's
PI2EQX4401 also provides power management Stand-by mode
operated by a Bus Enable pin.
Block Diagram
PI2EQX4401
2.5Gbps x1 Lane Serial PCI Express
Repeater/Equalizer with Clock Buffer
Pin Description
VDD
AI+
AI-
GND
AVDD
VDD
B0+
B0-
GND
VDD
VDD
A0+
A0-
GND
AGND
VDD
BI+
BI-
GND
IREF
NC
NC
SEL0_A
SEL1_A
SEL2_A
SEL3_A
EN_A
EN_B
OUT
-
OUT+
SEL3_B
SEL2_B
SEL1_B
SEL0_B
CLK
IN-
CLK
IN+
1
2
3
4
5
6
7
8
9
10
28
27
26
25
24
23
22
21
20
19
11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29
GND


2
PS8777B 02/15/06
PI2EQX4401
2.5Gbps x1 Lane Serial PCI Express
Repeater/Equalizer with Clock Buffer
Pin Description
Pin #
Pin Name
I/O
Description
1, 6, 10, 23, 28
V
DD
PWR
1.8V Supply Voltage
2
AI+
I
Positive CML Input Channel A with internal 50 pull down
3
AI-
I
Negative CML Input Channel A with internal 50 pull down
4, 9, 20, 25
GND
PWR
Supply Ground
22
BI+
I
Positive CML Input Channel B with internal 50 pull down
21
BI-
I
Negative CML Input Channel B with internal 50 pull down
33, 34
SEL[0:1]_A
I
Selection pins for equalizer (see Amplifier Configuration Table)
w/ 50K internal pull up
13, 14
SEL[0:1]_B
I
32
SEL[2]_A
I
Selection pins for amplifier (see Amplifier Configuration Table)
w/ 50K internal pull up
15
SEL[2]_B
I
31
SEL[3]_A
I
Selection pins for De-Emphasis (See De-Emphasis Configuration Table)
w/ 50K internal pull up
16
SEL[3]_B
I
27
AO+
O
Positive CML Output Channel A internal 50 pull up during normal operation and
2K pull up otherwise.
26
AO-
O
Negative CML Output Channel A with internal 50 pull up during normal opera-
tion and 2K pull up otherwise.
7
BO+
O
Positive CML Output Channel B with internal 50 pull up during normal operation
and 2K pull up otherwise.
8
BO-
O
Negative CMLOutput Channel B with internal 50 pull up during normal opera-
tion and 2K pull up otherwise.
30, 29
EN_[A,B]
I
EN_[A:B] is the enable pin. A LVCMOS high provides normal operation. A LVC-
MOS low selects a low power down mode.
12
CLKIN-
I
Differential Input Reference Clock
11
CLKIN+
I
17, 18
OUT+, OUT-
O
Differential Reference Clock Output
5
AVDD
PWR
1.8V Analog supply voltage
24
AGND
PWR
Analog ground
19
IREF
O
External 475 resistor connection to set the differential output current
35, 36
NC
N/A
No connect pins. For normal operation, leave pins floating
3
PS8777B 02/15/06
PI2EQX4401
2.5Gbps x1 Lane Serial PCI Express
Repeater/Equalizer with Clock Buffer
Storage Temperature........................................................ 65C to +150C
Supply Voltage to Ground Potential...................................0.5V to +2.5V
DC SIG Voltage.......................................................... 0.5V to V
CC
+0.5V
Current Output ................................................................-25mA to +25mA
Power Dissipation Continous......................................................... 500mW
Operating Temperature.............................................................. 0 to +70C
Output Swing Control
SEL2_[A:B]
Swing
0
1x
1
1.2x
Equalizer Selection
SEL0_[A:B]
SEL1_[A:B]
Compliance Channel
0
0
no equalization
0
1
[0:2.5dB] @ 1.25 GHz
1
0
[2.5:4.5dB] @ 1.25 GHz
1
1
[4.5:6.5dB] @ 1.25 GHz
Output De-emphasis Adjustment
SEL3_[A:B]
De-emphasis
0
0dB
1
-3.5dB
Note:
Stresses greater than those listed under MAXIMUM RAT-
INGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
4
PS8777B 02/15/06
PI2EQX4401
2.5Gbps x1 Lane Serial PCI Express
Repeater/Equalizer with Clock Buffer
AC/DC Electrical Characteristics
(V
DD
= 1.8 0.1V)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Ps
Supply Power
EN = LVCMOS Low
0.1
W
EN = LVCMOS High
0.3
Latency
From input to output
2.0
ns
CML Receiver Input
RL
RX
Return Loss
50 MHz to 1.25 GHz
12
dB
V
RX-DIFFP-P
Differential Input Peak-to-
peak Voltage
0.175
1.200
V
V
RX-CM-ACP
AC Peak Common Mode
Input Voltage
150
mV
Z
RX-DIFF-DC
DC Differential Input
Impedance
80
100
120
Z
RX-DC
DC Input Impedance
40
50
60
Equalization
J
RS
Residual Jitter
(1,2)
Total Jitter
0.3
Ulp-p
Deterministic jitter
0.2
J
RM
Random Jitter
(1,2)
1.5
psrms
Notes
1. K28.7 pattern is applied differentially at point A as shown in Figure 1.
2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 RJ + DJ) where RJ is random RMS jitter and DJ is maximum
deterministic jitter. Signal source is a K28.5 pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or
equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or
its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. JItter is measured at
0V at point C of Figure 1.
Figure 1. Test Condition Referenced in the Electrical Characteristic Table
5
PS8777B 02/15/06
PI2EQX4401
2.5Gbps x1 Lane Serial PCI Express
Repeater/Equalizer with Clock Buffer
AC/DC Electrical Characteristics
(T
A
= 0 to 70C)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
CML Transmitter Output (100 differential)
V
DIFFP
Output Voltage Swing
Differential Swing
| V
TX-D+
- V
TX-D-
|
400
900
mVp-p
V
TX-C
Common-Mode Voltage
| V
TX-D+
+ V
TX-D-
| / 2
V
CC
-
0.3
t
F
, t
R
Transition Time
20% to 80%
(1)
150
ps
Z
OUT
Output resistance
Single ended
40
50
60
Z
TX-DIFF-DC
DC Differential TX Impedance
80
100
120
C
TX
AC Coupling Capacitor
75
200
nF
V
TX-DIFFP-P
Differential Peak-to-peak Ouput
Voltage
V
TX-DIFFP-P
= 2 * | V
TX-D+
- V
TX-D-
|
0.8
1.8
V
LVCMOS Control Pins
V
IH
Input High Voltage
0.65
V
DD
V
V
IL
Input Low Voltage
0.35
V
DD
I
IH
Input High Current
250
A
I
IL
Input Low Current
500
Note:
1. Using K28.7 (0011111000) pattern)
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