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Datasheet: N18N3625P1B (NanoAmp Solutions)

Ftram, Pipeline, 36, 2.5, as Fast as 200, as Fast as 3.0, 100-TQFP, 119-PBGA, 165-FPBGA,

 

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NanoAmp Solutions
1
Stock No. 23275-A 6/03
N18N1825P1B N18N1833P1B
N18N3625P1B N18N3633P1B
NanoAmp Solutions, Inc.
1982 Zanker Road, San Jose, CA 95112
ph: 408-573-8878, FAX: 408-573-8877
www.nanoamp.com
This is an advance datasheet and subject to change without notice.
FTRAM is a trademark of NanoAmp Solutions, Inc.
NoBL is a trademark of Cycpress Semiconductor Corpopation
ZBT is a trademark of Integrated Device Technology
NtRAM is a trademark of Samsung Electronics Corporation
18Mb High Speed Synchronous Pipeline SRAMs with Fast bus Turn-
around FTRAM
TM
Architecture
Features
High performance pipeline operation
Cycle times up to 250MHz
Access times as fast as 2.6nS
Full 100% bus utilization
Fully compatible with other bus latency-
free SRAMs
Fully synchronous operation
Options for power supply
3.3V +10% and -5% or
2.5V +/- 5%
Separate I/O power supply of 3.3V or 2.5V
Individual byte write operation
Three chip enable signals
Simple depth expansion
ZZ mode for low power sleep mode
Mode pin for setting interleave or linear
burst mode of operation
JTAG Boundary Scan (BGA only)
JEDEC standard 100-pin TQFP, 165-ball
FPBGA and 119-ball PBGA packages
Functional Description
The N18N3625P1B, N18N3633P1B,
N18N1825P1B and N18N1833P1B are 18Mb high
performance synchronous SRAMs that are part of
a family of devices for those demanding high per-
formance. The FTRAM family of devices is
designed to operate without the need of NOP or
deselect clock cycles when transitioning from read
to write cycles and thereby allowing the use of all
available bandwidth. These high-speed devices
are fully compatible with other no bus turn-around
SRAMs such as NoBL
TM
, ZBT
TM
and NtRAM
TM
devices.
The memory devices contain 18Mb of memory
cells organized as 524,288 x 36 (N18N3625P1B,
N18N3633P1B) and 1,048,576 x 18
(N18N1825P1B, N18N1833P1B). The devices
operate in a synchronous manner with control sig-
nals, addresses and data inputs synchronized and
captured at the rising edge of clock for ease of use.
An asynchronous OE is available for disabling the
outputs at any time. An asynchronous ZZ signal
can be used to put the device into sleep mode with
all data retained. The devices are fabricated using
NanoAmp's advanced CMOS process and high-
speed/ultra low-power circuit technology.
The N18N3625P1B, N18N3633P1B,
N18N1825P1B and N18N1833P1B are ideal for
networking and communication systems where
high-density, high-performance memory elements
are required. The architecture allows the data bus
to be fully utilized when moving data into and out of
the SRAM.
Part number example:
N18N3625P1BQ-25C
Pipeline Performance and Power
SORT (MHz)
Unit
167
200
225
250
t
CYCLE
6.0
5.0
4.4
4.0
nS
t
ACCESS
3.4
3.0
2.8
2.6
nS
Icc
275
300
325
350
mA
Isb
70
70
70
70
mA
Options
Organization
512Kb x 36
N18N36
1Mb x 18
N18N18
Power supply
3.3V w/ Vddq = 3.3/2.5V
33
2.5V w/ Vddq = 2.5V
25
Operating Mode
Pipeline
P1
Package
100-pin TQFP
Q
119-ball PBGA
G
165-ball FPBGA
F
Speed
167MHz
16
200MHz
20
225MHz
22
250MHz
25
NanoAmp Solutions
2
Stock No. 23275-A 6/03
This is an advance datasheet and subject to change without notice.
N18N1825P1B N18N1833P1B
N18N3625P1B N18N3633P1B
100-Pin TQFP Packages
(1M x 18)
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQbP
NC
VSS
VDDQ
NC
NC
NC
A
NC
NC
VDDQ
VSS
NC
DQaP
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
CE1
CE2
NC
NC
BWb
BW
a
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV
A
A
A
A
LB
O
A
A
A
A
A1
A0
NC
NC
VS
S
VD
D
NC
NC
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
(512K x 36)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQcP
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQdP
DQbP
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQaP
A
A
CE1
CE2
BWd
BWc
BWb
BW
a
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV
A
A
A
A
LBO
A
A
A
A
A1
A0
NC
NC
VSS
VD
D
NC
NC
A
A
A
A
A
A
A
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
NanoAmp Solutions
3
Stock No. 23275-A 6/03
This is an advance datasheet and subject to change without notice.
N18N1825P1B N18N1833P1B
N18N3625P1B N18N3633P1B
119-Ball PBGA Packages
7 x 17 Ball BGA with 1.27 mm Ball Pitch
1Mb x 18
1
2
3
4
5
6
7
A
VDDQ
A
A
A
A
A
VDDQ
B
NC
CE2
A
ADV
A
CE3
NC
C
NC
A
A
VDD
A
A
NC
D
DQb
NC
VSS
NC
VSS
DQaP
NC
E
NC
DQb
VSS
CE1
VSS
NC
DQa
F
VDDQ
NC
VSS
OE
VSS
DQa
VDDQ
G
NC
DQb
BWb
A
VSS
NC
DQa
H
DQb
NC
VSS
WE
VSS
DQa
NC
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
NC
DQb
VSS
CLK
VSS
NC
DQa
L
DQb
NC
VSS
NC
BWa
DQa
NC
M
VDDQ
DQb
VSS
CKE
VSS
NC
VDDQ
N
DQb
NC
VSS
A1
VSS
DQa
NC
P
NC
DQbP
VSS
A0
VSS
NC
DQa
R
NC
A
LBO
VDD
NC
A
NC
T
NC
A
A
NC
A
A
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
512Kb x 36
1
2
3
4
5
6
7
A
VDDQ
A
A
A
A
A
VDDQ
B
NC
CE2
A
ADV
A
CE3
NC
C
NC
A
A
VDD
A
A
NC
D
DQc
DQcP
VSS
NC
VSS
DQbP
DQb
E
DQc
DQc
VSS
CE1
VSS
DQb
DQb
F
VDDQ
DQc
VSS
OE
VSS
DQb
VDDQ
G
DQc
DQc
BWc
A
BWb
DQb
DQb
H
DQc
DQc
VSS
WE
VSS
DQb
DQb
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
DQd
DQd
VSS
CLK
VSS
DQa
DQa
L
DQd
DQd
BWd
NC
BWa
DQa
DQa
M
VDDQ
DQd
VSS
CKE
VSS
DQa
VDDQ
N
DQd
DQd
VSS
A1
VSS
DQa
DQa
P
DQd
DQdP
VSS
A0
VSS
DQaP
DQa
R
NC
A
LBO
VDD
NC
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
NanoAmp Solutions
4
Stock No. 23275-A 6/03
This is an advance datasheet and subject to change without notice.
N18N1825P1B N18N1833P1B
N18N3625P1B N18N3633P1B
165-Ball FPBGA Packages
1M x 18
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CE1
BWb
NC
CE3
CKE
ADV
A
A
A
B
NC
A
CE2
NC
BWa
CLK
WE
OE
A
A
NC
C
NC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
DQaP
D
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
E
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
F
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
G
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
H
NC
VDD
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
J
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
K
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
L
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
M
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
N
DQbP
NC
VDDQ
VSS
NC
NC
NC
VSS
VDDQ
NC
NC
P
NC
NC
A
A
TDI
A1
TDO
A
A
A
NC
R
LBO
NC
A
A
TMS
A0
TCK
A
A
A
A
11 x 15 Ball BGA with 1.0 mm Ball Pitch
512K x 36
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CE1
BWc
BWb
CE3
CKE
ADV
A
A
NC
B
NC
A
CE2
BWd
BWa
CLK
WE
OE
A
A
NC
C
DQcP
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
DQbP
D
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
E
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
F
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
G
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
H
NC
VDD
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
J
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
K
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
L
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
M
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
N
DQdP
NC
VDDQ
VSS
NC
NC
NC
VSS
VDDQ
NC
DQaP
P
NC
NC
A
A
TDI
A1
TDO
A
A
A
NC
R
LBO
NC
A
A
TMS
A0
TCK
A
A
A
A
NanoAmp Solutions
5
Stock No. 23275-A 6/03
This is an advance datasheet and subject to change without notice.
N18N1825P1B N18N1833P1B
N18N3625P1B N18N3633P1B
Pin Descriptions
Signal
Type
POWER
A0, A1 Synch Input
Address inputs sampled at the rising edge of CLK. Least significant address
bits are used to set the internal burst counter (if used).
Ax
Synch Input
Address inputs 2 through 18/19, sampled at the rising edge of CLK.
LBO
Synch Input
Linear burst order, active low, used for setting the address order of the burst
counter. A low selects linear burst order while a high selects interleave burst
order and if floating, this input will default to a high (interleave order) This
should not be changed while operating the SRAM.
ADV
Synch Input
Advance/load, sampled at the rising edge of clock. When high, the internal
burst counter is advanced for the next address and when low, a new
address is loaded from the address pins.
BWa
BWb
BWc
BWd
Synch Input
Byte writes, active low, sampled at the rising edge of CLK if WE is low for a
write cycle. BWa controls byte a (DQa) inputs, BWb controls byte b (DQb)
inputs, BWc controls byte c (DQc) inputs and BWd controls byte d (DQd)
inputs. For x18 devices, only BWa and BWb apply.
WE
Synch Input
Write enable, active low, sampled at the rising edge of CLK. A low state ini-
tiates a write cycle.
CLK
Clock Input
Clock
CE1
Synch Input
Chip enable 1, active low, sampled on the rising edge of CLK. Used with
CE2 and CE3 and to select the device.
CE2
Synch Input
Chip enable 2, active high, sampled on the rising edge of CLK. Used with
CE1 and CE3 and to select the device.
CE3
Synch Input
Chip enable 3, active low, sampled on the rising edge of CLK. Used with
CE2 and CE1 and to select the device.
CKE
Synch Input
Clock enable, active low and while low, allows CLK to be recognized by the
SRAM. While high, CKE inhibits CLK from driving SRAM cycles and
extends cycles already in progress.
OE
Asynch Input
Output enable, asynchronous active low, tri-states the output buffers when
high and enables the output buffers when low.
ZZ
Asynch Input
Sleep mode, asynchronous active high, puts the device in a low power
sleep mode that retains all data while high. Defaults to an inactive low state.
DQa
DQb
DQc
DQd
Synch Input/
Output
During a write cycle, the data lines are synchronous inputs that are sampled
at the rising edge of CLK to specify data to be written to the memory array.
During a read cycle, the data lines are driven out with data from the SRAM
array. DQ(a, b, c, d) refer to the bytes a, b, c, d. For x18 devices, only DQa
and DQb apply.
VDD
Power Supply
Supplies power to the device core.
VDDQ I/O Power Supply Supplies power to the I/O section of the device.
VSS
Ground supply
Ground
TMS
Input
Test Mode Select supplies input command to the TAP controller with TCK.
TDI
Input
Test Data Input supplies serial input to test registers.
TDO
Output
Test Data Output supplies serial data out from test registers.
TCK
Input
Test Clock controls TAP controller and serial data in and data out.
NC
-
No connect
DNU
-
Do not use
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