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Datasheet: N02M083WL1AD (NanoAmp Solutions)

2mb Ultra-low Power Asynchronous Medical Cmos Sram 256kx8 Bit

 

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NanoAmp Solutions

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NanoAmp Solutions, Inc.
670 North McCarthy Blvd. Suite 220, Milpitas, CA 95035
ph: 408-935-7777, FAX: 408-935-7770
www.nanoamp.com
N02M083WL1A
Stock No. 23207-01 11/01/02
1
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
2Mb Ultra-Low Power Asynchronous Medical CMOS SRAM
256Kx8 bit
Overview
The N02M083WL1A is an integrated memory
device intended for non life-support (Class 1 or 2)
medical applications. This device comprises a 2
Mbit Static Random Access Memory organized as
262,144 words by 8 bits. The device is designed
and fabricated using NanoAmp's advanced CMOS
technology with reliability inhancements for
medical users. The base design is the same as
NanoAmp's N02M0818L2A, which has further
reliability processing for life-support (Class 3)
medical applications. The device operates with two
chip enable (CE1 and CE2) controls and output
enable (OE) to allow for easy memory expansion.
The N02M083WL1A is optimal for various
applications where low-power is critical such as
battery backup and hand-held devices. The device
can operate over a very wide temperature range of
-40
o
C to +85
o
C and is available in JEDEC
standard packages compatible with other standard
256Kb x 8 SRAMs
Product Family
Features
Single Wide Power Supply Range
2.3 to 3.6 Volts
Low standby current
3A maximum at 3.6V
Very low operating current
2 mA at 3.6V and 1Mhz (Typical)
Very low Page Mode operating current
0.5mA at 3.6V and 1Mhz (Typical)
Simple memory control
Dual Chip Enables (CE1 and CE2)
Output Enable (OE) for memory expansion
Low voltage data retention
Vcc = 1.8V
Automatic power down to standby mode
TTL compatible three-state output driver
Pin Configuration
Part Number
Package Type
Operating
Temperature
Power
Supply (Vcc)
Speed
Standby
Current
(I
SB
), Max
Operating
Current (Icc),
Max
N02M083WL1AN
32 - STSOP I
-40
o
C to +85
o
C
2.3V - 3.6V 70ns @ 2.3V
3.0 A
2.5 mA @ 1MHz
N02M083WL1AD Known Good Die
N02M083WL1A
STSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A9
A8
A13
WE
CE2
A15
V
CC
A17
A16
A14
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
V
SS
I/O2
I/O1
I/O0
A0
A1
A2
A3
Pin Descriptions
Pin Name
Pin Function
A
0
-A
17
Address Inputs
WE
Write Enable Input
CE1, CE2
Chip Enable Input
OE
Output Enable Input
I/O
0
-I/O
7
Data Inputs/Outputs
V
CC
Power
V
SS
Ground
2
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
Stock No. 23207-01 11/01/02
NanoAmp Solutions, Inc.
N02M083WL1A
Functional Block Diagram
Functional Description
CE1
CE2
WE
OE
I/O
0
- I/O
7
MODE
POWER
H
X
X
X
High Z
Standby
1
1. When the device is in standby mode, control inputs (WE and OE), address inputs and data input/outputs are internally isolated
from any external influence and disabled from exerting any influence externally.
Standby
X
L
X
X
High Z
Standby
1
Standby
L
H
L
X
2
2. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
Data In
Write
2
Active
L
H
H
L
Data Out
Read
Active
L
H
H
H
High Z
Active
Active
Capacitance
1
1. These parameters are verified in device characterization and are not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input Capacitance
C
IN
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
8
pF
I/O Capacitance
C
I/O
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
8
pF
Control
Logic
Page
Decode
Logic
Address
Inputs
A
4
- A
17
Input/
Output
Mux
and
Buffers
I/O
0
- I/O
7
Address
Word
Decode
Logic
Address
Address
Inputs
A
0
- A
3
16K Page
x 16 word
x 8 bit
RAM Array
Wo
r
d
M
u
x
CE1
CE2
WE
OE
3
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
Stock No. 23207-01 11/01/02
NanoAmp Solutions, Inc.
N02M083WL1A
Absolute Maximum Ratings
1
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Rating
Unit
Voltage on any pin relative to V
SS
V
IN,OUT
0.3 to V
CC
+0.3
V
Voltage on V
CC
Supply Relative to V
SS
V
CC
0.3 to 4.5
V
Power Dissipation
P
D
500
mW
Storage Temperature
T
STG
40 to 125
o
C
Operating Temperature
T
A
-40 to +85
o
C
Soldering Temperature and Time
T
SOLDER
240
o
C, 10sec(Lead only)
o
C
Operating Characteristics (Over Specified Temperature Range)
Item
Symbol
Test Conditions
Min.
Typ
1
1. Typical values are measured at Vcc=Vcc Typ., T
A
=25C and not 100% tested.
Max
Unit
Supply Voltage
V
CC
2.3
3.6
V
Data Retention Voltage
V
DR
Chip Disabled
3
1.8
V
Input High Voltage
V
IH
V
CC
-0.6
V
CC
+0.3
V
Input Low Voltage
V
IL
0.3
0.6
V
Output High Voltage
V
OH
I
OH
= 0.2mA
V
CC
0.2
V
Output Low Voltage
V
OL
I
OL
= -0.2mA
0.2
V
Input Leakage Current
I
LI
V
IN
= 0 to V
CC
0.5
A
Output Leakage Current
I
LO
OE = V
IH
or Chip Disabled
0.5
A
Read/Write Operating Supply Current
@ 1
s Cycle Time
2
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system.
I
CC1
V
CC
=3.6 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0
1.5
2.0
mA
Read/Write Operating Supply Current
@ 70 ns Cycle Time
2
I
CC2
V
CC
=3.6 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0
10.0
12.0
mA
Page Mode Operating Supply Current
@ 70 ns Cycle Time
2
(Refer to Power
Savings with Page Mode Operation
diagram)
I
CC3
V
CC
=2.3 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0
4.0
mA
Maximum Standby Current
3
I
SB1
V
IN
= V
CC
or 0V
Chip Disabled
t
A
= 85
o
C, V
CC
= 2.3 V
2.0
20.0
A
Maximum Data Retention Current
3
I
DR
V
CC
= 1.8V, V
IN
= V
CC
or 0
Chip Disabled, t
A
= 85
o
C
10.0
A
4
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
Stock No. 23207-01 11/01/02
NanoAmp Solutions, Inc.
N02M083WL1A
Power Savings with Page Mode Operation (WE = V
IH
)
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal
organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power
saving feature.
The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open
and 8-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant
bits and addressing the 16 words within the open page, power is reduced to the page mode value which is
considerably lower than standard operating currents for low power SRAMs.
Page Address (A4 - A17)
OE
CE1
CE2
Word Address (A0 - A3)
Open page
Word 1
Word 2
Word 16
...
5
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
Stock No. 23207-01 11/01/02
NanoAmp Solutions, Inc.
N02M083WL1A
Timing Test Conditions
Item
Input Pulse Level
0.1V
CC
to 0.9 V
CC
Input Rise and Fall Time
5ns
Input and Output Timing Reference Levels
0.5 V
CC
Output Load
CL = 30pF
Operating Temperature
-40 to +85
o
C
Timing
Item
Symbol
2.3 - 3.6 V
2.7 - 3.6 V
Units
Min.
Max.
Min.
Max.
Read Cycle Time
t
RC
100
70
ns
Address Access Time
t
AA
100
70
ns
Chip Enable to Valid Output
t
CO
100
70
ns
Output Enable to Valid Output
t
OE
35
35
ns
Chip Enable to Low-Z output
t
LZ
15
10
ns
Output Enable to Low-Z Output
t
OLZ
10
5
ns
Chip Disable to High-Z Output
t
HZ
0
30
0
20
ns
Output Disable to High-Z Output
t
OHZ
0
30
0
20
ns
Output Hold from Address Change
t
OH
15
10
ns
Write Cycle Time
t
WC
100
70
ns
Chip Enable to End of Write
t
CW
70
50
ns
Address Valid to End of Write
t
AW
70
50
ns
Write Pulse Width
t
WP
50
40
ns
Address Setup Time
t
AS
0
0
ns
Write Recovery Time
t
WR
0
0
ns
Write to High-Z Output
t
WHZ
30
20
ns
Data to Write Time Overlap
t
DW
50
40
ns
Data Hold from Write Time
t
DH
0
0
ns
End Write to Low-Z Output
t
OW
10
5
ns
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