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Datasheet: MTV048N (Myson Technology)

On-screen Display For Crt/lcd Monitor

 

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MTV048
On-Screen-Display Controller for CRT Monitor
sales@myson.com.tw
www.myson.com.tw
Rev. 1.2 January 2003
page 1 of 20
Myson Century, Inc.
Taiwan:
No. 2, Industry East Rd. III,
Science-Based Industrial Park, Hsin-Chu, Taiwan
Tel: 886-3-5784866 Fax: 886-3-5784349

USA:
4020 Moorpark Avenue Suite 115
San Jose, CA, 95117
Tel: 408-243-8388 Fax: 408-243-3188
GENERAL DESCRIPTION
MTV048 is designed for monitor applications to
display built-in fonts onto monitor screens. The
display operation occurs by transferring data and
controls information from the micro controller to RAM
through a serial data interface. It can execute a full-
screen display automatically, as well as specific
functions such as character background, bordering,
shadowing, blinking, double height and width, font-by-
font color control, button boxes, frame positioning,
frame size control by character height and row-to-row
spacing, horizontal display resolution, full-screen
erasing, fade-in/fade-out effect, windowing effect,
shadowing on window.
MTV048 provides 384 fonts including 360 standard
fonts, 16 multi-color fonts and 8 user fonts and 2 font
sizes, 12x16 or 12x18 for more efficacious
applications. The full OSD menu is formed by 15
rows x 30 columns, which can be positioned
anywhere on the monitor screen by changing vertical
or horizontal delay.
FEATURES
Software control for CRT applications.
On-chip PLL circuitry.
Horizontal SYNC input up to 150 KHz.
Programmable horizontal resolutions up to 1524
dots per display line.
Full screen display consists of 15 (rows) by 30
(columns).
12x16 or 12x18 dot matrix selection.
A total of 384 fonts including 360 standard fonts, 16
multi-color fonts and 8 user fonts.
8 color selections for character foreground,
background and window color.
Character button boxes with programmable box
length.
Character bordering, shadowing and blinking effect
for display.
Full-screen character double width control.
Double character height and/or width control per
row.
Programmable positioning for display screen center.
Row to row spacing control per row to avoid
expansion distortion.
4 programmable background windows with multi-
level operation and programmable shadow
width/height/color.
Software clear bit for full-screen erasing.
Programmable adaptive approach to handle H, V
sync collision automatically by hardware.
Fade-in/fade-out or blend-in/blend-out effects.
Compatible with SPI bus or I
2
C interface with
address 7AH (slave address is mask option).
5V or 3.3V power supply.
16-pin PDIP/SOP package.

BLOCK DIAGRAM
SERIAL DATA
INTERFACE
VERTICAL
DISPLAY CONTROL
HORIZONTAL
DISPLAY CONTROL
DISPLAY & ROW
CONTROL
REGISTERS
(RAM)
FONTS ROM &
USER FONTS RAM
WINDOWS & FRAME
CONTROL
COLOR ENCODER
PHASE LOCK LOOP
LUMINANCE & BORDER
GENERATOR
HFLB
VFLB
VCO
RP
SSB
SCK
SDA
ROUT
GOUT
BOUT
FBKG
INT
9 ROMADDR
R/WEN
8 DATA
VCLK
ROW
COLUMN
9 RAMADDR
LUMA
SHADOW
WINDOW
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MTV048
page 2 of 20
PIN CONNECTION












PIN DESCRIPTIONS
Name I/O Pin
No.
Descriptions
VSSA - 1 Analog ground. This ground pin is used for internal analog circuitry.
VCO / XIN
I/O
2
Voltage control oscillator. This pin is used to control the internal oscillator
frequency by DC voltage input from external low pass filter.
RP / NC
I/O
3
Bias Resistor (bit LCD = 0). The bias resistor is used to regulate the
appropriate bias current for internal oscillator to resonate at specific dot
frequency.
VDDA - 4 Analog power supply. Positive 5V / 3.3V DC supply for internal analog cir-
cuitry. And a 0.1uF decoupling capacitor should be connected across to
VDDA and VSSA.
HFLB I 5 Horizontal input. This pin is used to input the horizontal synchronizing
signal. It is a leading edge triggered and has an internal pull-up resistor.
SSB I 6
Serial interface enable. It is used to enable the serial data and is also used
to select the operation of I
2
C or SPI bus. If this pin is left floating, I
2
C bus
would be enabled. Otherwise the SPI bus is enabled.
SDA I 7
Serial data input. The external data transfer through this pin to internal
display registers and control registers. It has an internal pull-up resistor.
SCK I 8
Serial clock input. The clock-input pin is used to synchronize the data
transfer. It has an internal pull-up resistor.
VDD - 9
Digital power supply. Positive 5V / 3.3V DC supply for internal digital
circuitry and a 0.1uF decoupling capacitor should be connected across to
VDD and VSS.
VFLB I 10
Vertical input. This pin is used to input the vertical synchronizing signal. It
is leading triggered and has an internal pull-up resistor.
V33CAP I/O
11 3.3V Regulator Capacitor connection. Connect a decoupling capacitor to
VSS pin when DC supply = 5V, or connect to 3.3V directly when DC supply
= 3.3V.
FBKG O 12 Fast Blanking output. It is used to cut off external R, G, B signals of VGA
while this chip is displaying characters or windows.
BOUT O 13 Blue color output. It is a blue color video signal output.
GOUT O 14 Green color output. It is a green color video signal output.
ROUT O 15
Red color output. It is a red color video signal output.
VSS - 16
Digital ground. This ground pin is used for internal digital circuitry.

VSSA
VCO/XIN
VDDA
HFLB
SSB
SDA
SCK
RP/NC
VDD
VSS
ROUT
GOUT
FBKG
V33CAP
BOUT
VFLB
MTV048N /
MTV048P
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
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MTV048
page 3 of 20
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INTERFACE
The serial data interface receives data transmitted from an external controller. There are 2 types of buses, which
can be accessed through the serial data interface. One is SPI bus and the other is I
2
C bus.
i) SPI
bus
While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission
should start pulling SSB to "low" level, enabling MTV048 to receiving mode, and retain at "low" level till the last
cycle for a complete data packet transfer. The protocol is shown in Figure 1.
Figure-1 Data Transmission Protocol (SPI)
There are three transmission formats, shown as below:
Format (a) R - C - D
R - C - D
R - C - D .....
Format (b) R - C - D
C - D
C - D
C - D .....
Format (c) R - C - D
D
D
D
D
D .....
, where R=Row address, C=Column address, D=Display data
First byte
Last byte
SSB
SCK
SDA
MSB LSB
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MTV048
page 4 of 20
ii) I
2
C bus

I
2
C bus operation is only selected when SSB pin is left floating. And a valid transmission should start writing the
slave address 7AH to MTV048. The protocol is shown in Figure-2.
Figure-2 Data Transmission Protocol (I
2
C)
There are three transmission formats for I
2
C write mode, shown as below:
Format (a) S - R - C - D
R - C - D
R - C - D .....
Format (b) S - R - C - D
C - D
C - D
C - D .....
Format (c) S - R - C - D
D
D
D
D
D .....
, where S=Slave address, R=Row address, C=Column address, D=Display data
Each arbitrary length of data packet consists of 3 portions viz, Row address (R), Column address (C), and
Display data (D). Format (a) is suitable for updating small amount of data, which will be allocated with a different
row address and column address. Format (b) is recommended for updating data that has the same row address
but a different column address. Massive data updating or full screen data change should use format (c) to
increase transmission efficiency. The row and column address will be incremented automatically when the for-
mat (c) is applied. Furthermore, the undefined locations in display or user fonts RAM should be filled with
dummy data.

Table-1 The Configuration of Transmission Formats
Address b7 b6 b5 b4 b3 b2 b1 b0 Format
Row
1 0 0 R4 R3 R2 R1 R0 a,b,c
Column
ab
0 0 D8
C4 C3 C2 C1 C0 a,b
Column
c
0 1 D8
C4 C3 C2 C1 C0
c
Address Bytes of
Display Reg.
Data
D7 D6 D5 D4 D3 D2 D1 D0 a,b,c
Row
1 0 1 R4 R3 R2 R1 R0 a,b,c
Column
ab
0 0 x C4 C3 C2 C1 C0 a,b
Column
c
0 1 x C4 C3 C2 C1 C0
c
Attribute Bytes of
Display Reg.
Data
D7 D6 D5 D4 D3 D2 D1 D0 a,b,c
Row
1 1 - - - R2
R1
R0 a,b,c
Column
ab
0 0 C5 C4 C3 C2 C1 C0 a,b
Column
c
0 1 C5 C4 C3 C2 C1 C0
c
User Fonts
Data
D7 D6 D5 D4 D3 D2 D1 D0 a,b,c

There are 3 types of data, which should be accessed through the serial data interface. One is ADDRESS bytes
of display registers, another is ATTRIBUTE bytes of display registers, and the other is user fonts RAM data.
The protocols are all the same except the bit6 and bit5 of row address and the bit5 of column address. The MSB
(b7) is used to distinguish row and column addresses when transferring data from external controller. The bit6 of
SCK
SDA
first byte
START
ACK
second byte
last byte
ACK
STOP
B7
B6
B0
B7
B0
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MTV048
page 5 of 20
row address is used to distinguish display registers and user fonts RAM data and the bit6 of column address is
used to differentiate the column address for format (a), (b) and format (c) respectively. Bit5 of row address for
display register is used to distinguish ADDRESS byte when it is set to "0" and ATTRIBUTE byte when it is set to
"1". And at address bytes, bit5 of column address is the MSB (bit8) and data bytes are the 8 LSB
(bit7~bit0) of display fonts address
to save half MCU memory for true 392 fonts display. So each one of the
384 fonts can be displayed at the same time. See Table 1. And for format (c), since D8 is filled while program
column address of address bytes, the continued data will be the same bank of upper 128 fonts or lower 256
fonts until program column address is of address bytes again.
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format
(a), but not from format (c) back to format (a) and (b). The alternation between transmission formats is config-
ured as the state diagram shown in Figure-3 .
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