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Datasheet: MTV030 (Myson Technology)

On-screen Display For Crt/lcd With Auto-sizing

 

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This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
1/21
MTV030 Revision 1.0 10/15/1999
MTV030
MYSON
TECHNOLOGY
FEATURES
GENERAL DESCRIPTION
BLOCK DIAGRAM
Horizontal SYNC input up to 150 KHz.
On-chip PLL circuitry up to 150 MHz.
Minimum timing measurement among HFLB, VFLB, RIN,
GIN and BIN for auto sizing.
Full screen self-test pattern generator.
Programmable Hor. resolutions up to 1524 dots per line.
Full-screen display consists of 15 (rows) by 30 (columns)
Two font size 12x16 or 12x18 dot matrix per character.
True totally 512 mask ROM fonts including 496 standard
fonts and 16 multi-color fonts.
Double character height and/or width control.
Programmable positioning for display screen center.
Character bordering, shadowing and blinking effect.
Programmable character height (18 to 71 lines) control.
Row to row spacing control to avoid expansion distortion.
4 programmable windows with multi-level operation.
Shadowing on windows with programmable shadow
width/height/color.
Programmable adaptive approach to handle H, V sync
collision automatically by hardware.
Software clears bit for full-screen erasing.
Fade-in/fade-out or blending-in/blending-out effects.
5-channel/8-bit PWM D/A converter output.
Compatible with SPI bus or I
2
C interface with slave
address 7AH/7BH (slave address is mask option).
16-pin, 20-pin or 24-pin PDIP package.
On-Screen Display with Auto-Sizing Controller
MTV030 is designed for monitor applications to display
built-in characters or fonts onto monitor screens. The dis-
play operation occurs by transferring data and control infor-
mation from the micro-controller to RAM through a serial
data interface. It can execute full-screen display automati-
cally, as well as specific functions such as character back-
ground, bordering, shadowing, blinking, double height and
width, font by font color control, frame positioning, frame
size control by character height and row-to-row spacing,
horizontal display resolution, full-screen erasing, fade-in/
fade-out effect, windowing effect, shadowing on window
and full-screen self-test pattern generator.
MTV030 provides true 512 fonts including 496 standard
fonts and 16 multi-color fonts and 2 font sizes, 12x16 or
12x18 for more efficacious applications. So each one of the
512 fonts can be displayed at the same time. The full OSD
menu is formed by 15 rows x 30 columns, which can be
positioned anywhere on the monitor screen by changing
vertical or horizontal delay.
The auto sizing video measurement module measure
the timing relationship among HFLB, VFLB, and R, G, BIN
at the speed related to the OSD resolution. MCU can get
the measurement data, active video, front porth and back
porth, through I
2
C bus read/write operation to keep the
appropriate display size and center.
SERIAL DATA
INTERFACE
ADDRESS BUS
ADMINISTRATOR
VERTICAL
DISPLAY
CONTROL
DISPLAY & ROW
CONTROL
REGISTERS
COLOUR
ENCODER
WINDOWS &
FRAME
CONTROL
WR
WG
WB
FBKGC
BLANK
LUMAR
LUMAG
LUMAB
BLINK
VCLKX
DATA
VERTD
HORD
CH
8
8
7
BSEN
SHADOW
OSDENB
HSP
VSP
HORIZONTAL
DISPLAY CONTROL
PHASE LOCK LOOP
8
DATA
LPN
CWS
VCLKS
5
DATA
CWS
CHS
8
LUMAR
LUMAG
LUMAB
BLINK
CRADDR
8
LUMA
BORDER
ARWDB
HDREN
VCLKX
HORD 8
CH
CHS
VERTD
7
8
LPN
NROW
VDREN
5
RCADDR
DADDR
FONTADDR
WINADDR
PWMADDR
5
9
9
5
5
ARWDB
HDREN
VDREN
NROW
DATA
ROW, COL
ACK
8
9
CHARACTER ROM
LUMINANCE &
BORDGER
GENERATOR
VDD
VSS
VDDA
VSSA
ROUT
GOUT
BOUT
FBKG
HTONE
HFLB
RP
VCO
VFLB
SSB
SCK
SDA
VSP
HSP
PWM D/A
CONVERTER
PWM0
PWM1
PWM2
PWM3
PWM4
8
DATA
8
POWER ON RESET
PRB
AUTO SIZING
MEASUREMENT
RIN
GIN
BIN
DATA 8
2/21
MTV030 Revision 1.0 10/15/1999
MTV030
MYSON
TECHNOLOGY
1.0 PIN CONNECTION
2.0 PIN DESCRIPTIONS
Name
I/O
Pin No.
Descriptions
N16 N201 N202 N24
VSSA
-
1
1
1
1
Analog ground. This ground pin is used to internal analog cir-
cuitry.
VCO
I/O
2
2
2
2
Voltage Control Oscillator. This pin is used to control the
internal oscillator frequency by DC voltage input from external
low pass filter.
RP
I/O
3
3
3
3
Bias Resistor. The bias resistor is used to regulate the appro-
priate bias current for internal oscillator to resonate at specific
dot frequency.
VDDA
-
4
4
4
4
Analog power supply. Positive 5 V DC supply for internal
analog circuitry. And a 0.1uF decoupling capacitor should be
connected across to VDDA and VSSA.
HFLB
I
5
5
5
5
Horizontal input. This pin is used to input the horizontal syn-
chronizing signal. It is a leading edge triggered and has an
internal pull-up resistor.
VSSA
VCO
RP
VDDA
HFLB
SSB
SDA
SCK
VSS
ROUT
GOUT
BOUT
FBKG
INT
VFLB
VDD
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
MT
V030N-xx
VSSA
VCO
RP
VDDA
HFLB
SSB
SDA
SCK
RIN
GIN
BIN
PWM0
VSS
ROUT
GOUT
BOUT
FBKG
INT
VFLB
VDD
PWM4
PWM3
PWM2
PWM1
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
MT
V030
N24-xx
VSSA
VCO
RP
VDDA
HFLB
SSB
SDA
SCK
PWM0
PWM1
VSS
ROUT
GOUT
BOUT
FBKG
INT
VFLB
VDD
PWM3
PWM2
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
M
T
V030N201
-xx
VSSA
VCO
RP
VDDA
HFLB
SSB
SDA
SCK
RIN
GIN
VSS
ROUT
GOUT
BOUT
FBKG
INT
VFLB
VDD
NC
BIN
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
MT
V
030N202-xx
3/21
MTV030 Revision 1.0 10/15/1999
MTV030
MYSON
TECHNOLOGY
SSB
I
6
6
6
6
Serial interface enable. It is used to enable the serial data
and is also used to select the operation of I
2
C or SPI bus. If
this pin is left floating, I
2
C bus is enabled, otherwise the SPI
bus is enabled.
SDA
I
7
7
7
7
Serial data input. The external data transfer through this pin to
internal display registers and control registers. It has an inter-
nal pull-up resistor.
SCK
I
8
8
8
8
Serial clock input. The clock-input pin is used to synchronize
the data transfer. It has an internal pull-up resistor.
RIN
I
-
-
9
9
Red video input. It is used for auto sizing measurement and
this signal is came from video pre-amp red output.
GIN
I
-
-
10
10
Green video input. It is used for auto sizing measurement and
this signal is came from video pre-amp green output.
BIN
I
-
-
11
11
Blue video input. It is used for auto sizing measurement and
this signal is came from video pre-amp blue output.
NC
-
-
-
12
-
No connection.
PWM0
O
-
9
-
12
Open-Drain PWM D/A converter 0. The output pulse width is
programmable by the register of Row 15, Column 23.
PWM1
O
-
10
-
13
Open-Drain PWM D/A converter 1. The output pulse width is
programmable by the register of Row 15, Column 24.
PWM2
O
-
11
-
14
Open-Drain PWM D/A converter 2. The output pulse width is
programmable by the register of Row 15, Column 25.
PWM3
O
-
12
-
15
Open-Drain PWM D/A converter 3. The output pulse width is
programmable by the register of Row 15, Column 26.
PWM4
O
-
-
-
16
Open-Drain PWM D/A converter 4. The output pulse width is
programmable by the register of Row 15, Column 27.
VDD
-
9
13
13
17
Digital power supply. Positive 5 V DC supply for internal digi-
tal circuitry and a 0.1uF decoupling capacitor should be con-
nected across to VDD and VSS.
VFLB
I
10
14
14
18
Vertical input. This pin is used to input the vertical synchroniz-
ing signal. It is leading triggered and has an internal pull-up
resistor.
INT
O
11
15
15
19
Intensity color output. 16-color selection is achievable by
combining this intensity pin with R/G/B output pins.
FBKG
O
12
16
16
20
Fast Blanking output. It is used to cut off external R, G, B sig-
nals of VGA while this chip is displaying characters or win-
dows.
BOUT
O
13
17
17
21
Blue color output. It is a blue color video signal output.
GOUT
O
14
18
18
22
Green color output. It is a green color video signal output.
ROUT
O
15
19
19
23
Red color output. It is a red color video signal output.
VSS
-
16
20
20
24
Digital ground. This ground pin is used to internal digital cir-
cuitry.
Name
I/O
Pin No.
Descriptions
N16 N201 N202 N24
4/21
MTV030 Revision 1.0 10/15/1999
MTV030
MYSON
TECHNOLOGY
3.0 FUNCTIONAL DESCRIPTIONS
3.1 SERIAL DATA INTERFACE
The serial data interface receives data transmitted from an external controller. And there are 2 types of bus
can be accessed through the serial data interface, one is SPI bus and other is I
2
C bus.
3.1.1 SPI bus
While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission
should be starting from pulling SSB to "low" level, enabling MTV030 to receiving mode, and retain "low" level
until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1.
There are three transmission formats shown as below:
Format (a) R - C - D
R - C - D
R - C - D .....
Format (b) R - C - D
C - D
C - D
C - D .....
Format (c) R - C - D
D
D
D
D
D .....
Where R=Row address, C=Column address, D=Display data
3.1.2 I
2
C bus
I
2
C bus operation is only selected when SSB pin is left floating. And a valid transmission should be starting
from writing the slave address 7AH(write mode), or 7BH(read mode) to MTV030. The protocol is shown in
Figure 2. And the auto sizing video measurement data (total 10 bytes) are read only registers and the others
are write only registers.
There are three transmission formats for I
2
C write mode shown as below:
Format (a) S - R - C - D
R - C - D
R - C - D .....
Format (b) S - R - C - D
C - D
C - D
C - D .....
Format (c) S - R - C - D
D
D
D
D
D .....
Where S=Slave address, R=Row address, C=Column address, D=Display data
And there is one transmission format for I
2
C read mode shown as below:
Format (a) S
D
D
D
D
D
D
D
D
D
D
dummy D
dummy D .....
Where S=Slave address, D=Measurement data
MSB
LSB
SSB
SCK
SDA
first byte
last byte
FIGURE 1. Data Transmission Protocol (SPI)
FIGURE 2. Data Transmission Protocol (I
2
C)
SCK
SDA
first byte
START
ACK
second byte
last byte
ACK
STOP
B7
B6
B0
B7
B0
5/21
MTV030 Revision 1.0 10/15/1999
MTV030
MYSON
TECHNOLOGY
In the I
2
C read mode, 10 bytes of auto sizing video measurement data will be output directly from byte 0 to
byte 9 and continues with dummy data until stop condition occurred when I
2
C R/W bit is set to "1".
Each arbitrary length of data packet consists of 3 portions viz, Row address (R), Column address (C), and
Display data (D). Format (a) is suitable for updating small amount of data which will be allocated with different
row address and column address. Format (b) is recommended for updating data that has same row address
but different column address. Massive data updating or full screen data change should use format (c) to
increase transmission efficiency. The row and column address will be incremented automatically when the for-
mat (c) is applied. Furthermore, the undefined locations in display or fonts RAM should be filled with dummy
data.
There are 2 types of data should be accessed through the serial data interface, one is ADDRESS bytes of dis-
play registers, and other is ATTRIBUTE bytes of display registers, the protocol are same for all except the bit5
of row address and the bit5 of column address. The MSB(b7) is used to distinguish row and column
addresses when transferring data from external controller. The bit6 of column address is used to differentiate
the column address for format (a), (b) and format (c) respectively. Bit5 of row address for display register is
used to distinguish ADDRESS byte when it is set to "0" and ATTRIBUTE byte when it is set to "1". And at
address bytes, bit5 of column address is the MSB (bit8) and data bytes are the 8 LSB (bit7~bit0) of dis-
play fonts address
to save half MCU memory for true 512 fonts. So each one of the 512 fonts can be dis-
played at the same time. See Table 1. And for format (c), since D8 is filled while program column address of
address bytes, the continued data will be the same bank of upper 256 fonts or lower 256 fonts until program
column address of address bytes again.
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format
(a) and (c), but not from format (c) back to format (a) and (b). The alternation between transmission formats is
configured as the state diagram shown in Figure 3.
3.2 Address bus administrator
The administrator manages bus address arbitration of internal registers or user fonts RAM during external
data write in. The external data write through serial data interface to registers must be synchronized by inter-
nal display timing. In addition, the administrator also provides automatic increment to address bus when exter-
nal write using format (c).
3.3 Vertical display control
The vertical display control can generates different vertical display sizes for most display standards in current
monitors. The vertical display size is calculated with the information of double character height bit(CHS), verti-
TABLE 1. The configuration of transmission formats.
Address
b7
b6
b5
b4
b3
b2
b1
b0
Format
Address Bytes
of Display Reg.
Row
1
0
0
R4
R3
R2
R1
R0
a,b,c
Column
ab
0
0
D8
C4
C3
C2
C1
C0
a,b
Column
c
0
1
D8
C4
C3
C2
C1
C0
c
Data
D7
D6
D5
D4
D3
D2
D1
D0
a,b,c
Attribute Bytes
of Display Reg.
Row
1
0
1
R4
R3
R2
R1
R0
a,b,c
Column
ab
0
0
x
C4
C3
C2
C1
C0
a,b
Column
c
0
1
x
C4
C3
C2
C1
C0
c
Data
D7
D6
D5
D4
D3
D2
D1
D0
a,b,c
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