HTML datasheet архив (поиск документации на электронные компоненты) Поиск даташита (1.687.043 компонентов)
Где искать

Datasheet: MTV016-N (Myson Technology)

Enhanced On-screen Display Controller

 

Скачать: PDF   ZIP
 
MYSON
TECHNOLOGY
MTV016
Enhanced On-Screen-Display Controller
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification
without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the
product.
MTV016 Revision 2.0 01/01/1999
1/11
FEATURES
Horizontal SYNC input up to 100 KHz.
On-chip PLL circuitry up to a 90 MHz pixel rate for multi-SYNC operation.
Programmable horizontal resolutions up to 1524 dots per display row.
538-byte display registers to control full screen display.
Full screen display consists of 10 (rows) by 24 (columns) characters.
12 x 18 dot matrix per character.
128 built-in characters and graphic symbols, and character by character color selection.
Maximum of 8 colors selectable per display row.
Double character height and/or width control.
Programmable positioning for display screen center.
Bordering and shadowing effect for display.
Programmable vertical character height (18 to 71 lines) for multi-SYNC operation.
4 programmable background windows with multi-level windowing effect.
Software clear function for display frame buffer.
HSYNC and VSYNC input polarity selectable.
Auto detection for input edge distortion between HSYNC and VSYNC inputs.
Half tone and fast blanking output.
Software force blank function for display frame.
Compatible with both SPI bus and I
2
C interface through pin selection.
16-pin PDIP package.
GENERAL DESCRIPTION
MTV016 is designed for use in monitor applications to display the built-in characters or symbols onto a
monitor screen. The display operation occurs by transferring data and control information in the micro-
controller to RAM through a serial data interface. It can execute a full screen display automatically and
specific functions such as character bordering, shadowing, double height and width, font by font color
control, frame positioning, frame size control by character height and horizontal display resolution, and
windowing effect.
BLOCK DIAGRAM
SERIAL DATA
INTERFACE
ADDRESS BUS
ADMINISTRATOR
VERTICAL
DISPLAY
CONTROL
DISPLAY & ROW
CONTROL
REGISTERS
COLOUR
ENCODER
WINDOWS &
FRAME
CONTROL
WR
WG
WB
CCS2
FBKGC
BLANK
CCS0
CCS1
BLINK
VCLKX
DATA
VERTD
HORD
CH
8
8
7
BSEN
SHADOW
OSDENB
HSP
VSP
HORIZONTAL
DISPLAY CONTROL
PHASE LOCK LOOP
8
LPN
CWS
VCLKS
5
DATA
CWS
CHS
5
CCS0
CCS1
BLINK
CRADDR
7
LUMA
BORDER
ARWDB
HDREN
VCLKX
HORD 7
CH
CHS
VERTD
7
8
LPN
NROW
VDREN
5
RCADDR
DADDR
WADDR
5
9
5
ARWDB
HDREN
VDREN
NROW
DATA
DAEN
RAEN,CAEN
8
2
CHARACTER ROM
LUMINANCE &
BORDGER
GENERATOR
VDD
VSS
VDDA
VSSA
ROUT
GOUT
BOUT
FBKG
HTONE
HFLB
RP
VCO
VFLB
SSB
SCK
SDA
VSP
HSP
MYSON
TECHNOLOGY
MTV016
MTV016 Revision 2.0 01/01/1999
2/11
1.0 CONNECTION DIAGRAM
(16-PIN PDIP 300 MIL PACKAGE)
VSSA
VCO
RP
VDDA
HFLB
SSB
SDA
SCK
MTV016-N
VSS
ROUT
GOUT
BOUT
FBKG
HTONE
VFLB
VDD
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
2.0 PIN DESCRIPTIONS
Name
I/O
Pin#
Function
VSSA
-
1
Analog Ground. Used for internal analog circuitry.
VCO
I/O
2
Voltage Control Oscillator. Used to control the internal oscillator
frequency by DC voltage input from an external low pass filter.
RP
I/O
3
Bias Resistor. Used to regulate the appropriate bias current for the
internal oscillator to resonate at a specific dot frequency.
VDDA
-
4
Analog Power Supply. Positive 5 V DC supplies for internal analog
circuitry. A 0.1uF decoupling capacitor should be connected across
VDDA and VSSA.
HFLB
I
5
Horizontal Input. Used to input the horizontal synchronizing signal. It is
negative edge triggered and has an internal 100 k
pull-up resistor.
SSB
I
6
Serial Interface Enable. Used to enable the serial data and to select I
2
C
or SPI bus operation. If this pin is left floating, the I
2
C bus is enabled,
otherwise the SPI bus is enabled.
SDA
I
7
Serial Data Input. Transfers data through this pin to the internal display
and control registers. It has an internal 100 k
pull-up resistor.
SCK
I
8
Serial Clock Input. Used to synchronize the data transfer. It has an
internal 100 k
pull-up resistor.
VDD
-
9
Digital Power Supply. Positive 5 V DC supply for internal digital circuitry
and a 0.1uF decoupling capacitor should be connected across VDD and
VSS.
VFLB
I
10
Vertical Input. Used to input the vertical synchronizing signal. It is
negative triggered and has an internal pull-up resistor.
HTONE
O
11
Half Tone Output. Used to attenuate the external R, G, B amplifiers gain
for the transparent windowing effect.
FBKG
O
12
Fast Blanking Output. Used to cut off the external R, G, B signals while
this chip is displaying characters or windows.
BOUT
O
13
Blue Color Output. A blue color video signal output.
GOUT
O
14
Green color output. It is a green color video signal output.
ROUT
O
15
Red Color Output. A red color video signal output.
VSS
-
16
Digital Ground. Used for internal digital circuitry.
MYSON
TECHNOLOGY
MTV016
MTV016 Revision 2.0 01/01/1999
3/11
3.0 FUNCTIONAL DESCRIPTIONS
3.1 Serial Data Interface
The serial data interface receives data transmitted from an external controller. There are 2 types of bus
that can be accessed through the serial data interface: SPI bus and I
2
C bus.
3.1.1 SPI Bus
While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. A valid transmission
should be started by pulling SSB to "low" level, enabling MTV016 in receiving mode, and retaining "low"
level until the last cycle for a complete data packet transfer. The protocol is shown in Figure 2:
Figure 2. Data Transmission Protocol
There are 3 transmission formats as shown below:
Format (a) R - C - D
R - C - D
R - C - D ..........
Format (b) R - C - D
C - D
C - D
C - D .......
Format (c) R - C - D
D
D
D
D
D .........
R=row address, C=column address, D=display data
3.1.2 I
2
C Bus
The I
2
C bus operation is only selected when the SSB pin is left floating. A valid transmission should
begin by writing the slave address 7AH, which is the mask option, to MTV016. The protocol is shown in
Figure 3:
SCK
SDA
fist byte
START
ACK
second byte
last byte
ACK
STOP
B7
B6
B0
B7
B0
Figure 3. Data Transmission Protocol (I
2
C)
There are 3 transmission formats as shown below:
Format (a) S - R - C - D
R - C - D
R - C - D ..........
Format (b) S - R - C - D
C - D
C - D
C - D .......
Format (c) S - R - C - D
D
D
D
D
D ........
S=slave address, R=row address, C=column address, D=display data
Each arbitrary length of data packet consists of 3 portions: row address (R), column address (C) and
display data (D). Format (a) is suitable for updating small amounts of data, which will be allocated to
different row and column addresses. Format (b) is recommended for updating data that has the same
row address but a different column address. Massive data updating or a full screen data change should
use format (c) to increase transmission efficiency. The row and column address will be incremented
automatically when format (c) is applied. Furthermore, the undefined locations in display or font RAM
should be filled with dummy data.
MS
B
LSB
SSB
SCK
SDA
first byte
last byte
MYSON
TECHNOLOGY
MTV016
MTV016 Revision 2.0 01/01/1999
4/11
There are 2 types of data that should be accessed through the serial data interface: ADDRESS bytes and
ATTRIBUTE bytes. The protocol is the same for both except for bit 6 of the row address. The MSB (b7)
bit is used to distinguish row and column addresses when transferring data from the external controller.
Bit 6 of the row address is used to distinguish the ADDRESS byte when it is set to "0" and the
ATTRIBUTE byte when it is set to "1", or to differentiate the column address for formats (a), (b) and (c),
respectively. The configuration of transmission formats is shown in Table 1:
Table 1. Configuration of Transmission Formats
Address
b7
b6
b5
b4
b3
b2
b1
b0
Format
Row
1
0
x
x
R3
R2
R1
R0
a,b,c
Columnab
0
0
x
C4
C3
C2
C1
C0
a,b
ADDRESS
BYTES
Columnc
0
1
x
C4
C3
C2
C1
C0
c
Row
1
1
x
x
R3
R2
R1
R0
a,b,c
Columnab
0
0
x
C4
C3
C2
C1
C0
a,b
ATTRIBUTE
BYTES
Columnc
0
1
x
C4
C3
C2
C1
C0
c
Initiate
ROW
COL
c
COL
ab
DA
c
DA
ab
1, X
0, 1
0, 0
X, X
X, X
0, 1
1, X
1, X
format (a)
format (b)
format (c)
X, X
0, X
Input = b7, b6
0, 0
Figure 4. Transmission State Diagram
The data transmission is permitted to change from format (a) to formats (b) and (c), or from format (b) to
format (a), but not from format (c) back to formats (a) and (b). The alternation between formats is
configured as the state diagram shown in Figure 4.
3.2 Address Bus Administrator
The administrator manages bus address arbitration of internal registers during external data writing. The
external data, which is written to registers through the serial data interface, must be synchronized by
internal display timing. In addition, the administrator also provides automatic incrementing to the address
bus when external writing using format (c).
3.3 Vertical Display Control
The vertical display control can generate different vertical display sizes for most display standards in
current monitors. The vertical display size is calculated with the information of the double character
height bit (CHS) and the vertical display height control register (CH6-CH0). The algorithm of repeating
character line displays is shown in Tables 2 and 3. The programmable vertical size range is 180 lines to
a maximum of 1420 lines.
MYSON
TECHNOLOGY
MTV016
MTV016 Revision 2.0 01/01/1999
5/11
The vertical display center for a full screen display may be figured out according to the information of the
vertical starting position register (VERTD) and VFLB input. The vertical delay starting from the leading
edge of VFLB is calculated using the following equation:
vertical delay time = (VERTD * 4 + 1) * H
H = one horizontal line display time
Table 2. Repeat Line Weight of Character
CH6 - CH0
Repeat Line Weight
CH6,CH5=11
+18*3
CH6,CH5=10
+18*2
CH6,CH5=0x
+18
CH4=1
+16
CH3=1
+8
CH2=1
+4
CH1=1
+2
CH0=1
+1
Table 3. Repeat Line Number of Character
Repeat Line #
Repeat Line
Weight
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
+1
-
-
-
-
-
-
-
-
v
-
-
-
-
-
-
-
-
-
+2
-
-
-
-
v
-
-
-
-
-
-
-
v
-
-
-
-
-
+4
-
-
v
-
-
-
v
-
-
-
v
-
-
-
v
-
-
-
+8
-
v
-
v
-
v
-
v
-
v
-
v
-
v
-
v
-
-
+16
-
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
-
+17
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
-
+18
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Note:" v " means the nth line in the character would be repeated once, while " - " means the nth line in the character would not be
repeated.
3.4 Horizontal Display Control
The horizontal display control is used to generate control timing for horizontal displays based on double
character width bit (CWS), horizontal positioning register (HORD), horizontal resolution register (HORR)
and HFLB input. A horizontal display line consists of (HORR*12) dots, including 288 dots for 24 display
characters; the remaining dots are for a blank region. The horizontal delay starting from the HFLB
leading edge is calculated using the following equation:
horizontal delay time = (HORD * 6 + 49) * P - phase error detection pulse width
P = one pixel display time = one horizontal line display time / (HORR*12)
3.5 Phase Lock Loop (PLL)
On-chip PLL generates system clock timing (VCLK) by tracking the input HFLB and horizontal resolution
register (HORR). The frequency of VCLK is determined using the following equation:
VCLK Freq = HFLB Freq * HORR * 12
The VCLK frequency ranges from 5MHz to 90MHz and is selected by VCO1and VCO0. In addition, when
HFLB input is not present for MTV016, the PLL will generate a specific system clock, approximately
2.5MHz, by a built-in oscillator to ensure data integrity.
3.6 Display & Row Control Registers
The internal RAM contains display and row control registers. The display registers have 240 locations
that are allocated between row 0/column 0 and row 9/column 23, as shown in Figure 5. Each display
© 2018 • ChipFind
Контакты
Главная страница