HTML datasheet архив (поиск документации на электронные компоненты) Поиск даташита (1.687.043 компонентов)
Где искать

Datasheet: MTV004 (Myson Technology)

On-screen Display Shrink Version

 

Скачать: PDF   ZIP
 
MYSON
TECHNOLOGY
MTV004
On-Screen Display Shrink Version
This data sheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
MTV004 Revision 4.0 06/24/1999
1/9
FEATURES



On-chip phase lock loop circuitry for multi-sync operation.



Horizontal input up to 100 KHz.



273-byte display registers to control full screen display.



Full screen display consisting of 10 rows by 24 characters.



128 alphanumeric characters or graphic symbols built in character ROM.



12 x 16 dot matrix per character.



Character by character color selection.



4 color selections in a total of 8 color combinations per row.



4-character size options available by doubling character height and/or width.



Programmable positioning for display screen center.



Character bordering and shadowing.



Programmable vertical character height for multi-sync operation.



Multi-level windowing effect.



Half tone and fast blanking output.



Compatible with both SPI bus and I
2
C interface through pin selection.



16-pin PDIP package.
GENERAL DESCRIPTION
MTV004 is designed for use in monitor applications to display the built-in characters or symbols onto the
monitor screen. The display operation is enabled by transferring data and control information in the
microcontroller to RAM through a serial data interface. It can execute the full screen display automatically as
well as some specific functions such as character bordering, shadowing, double height, double width and color
control, frame positioning, vertical display height, and windowing effect.
BLOCK DIAGRAM
SERIAL DATA
INTERFACE
ADDRESS BUS
ADMINISTRATOR
VERTICAL
CONTROL
LOGIC
DISPLAY
REGISTERS
(RAM)
COLOR
ENCODER
WINDOWS &
FRAME
CONTROL
WWR
WWG
WWB
C(R,G,B)*4
WACTIVE
CCS1
CCS0
DATA
WACTIVE
CCS1
CH 6
BSEN
SHADOW
VERTD
HORD
OSDENB
HORIZONTAL
CONTROL LOGIC
PHASE LOCK LOOP
8
LP1/2
VCLK
2
CWS
CHS
C(R,G,B)*4
CCS0
CRADDR
7
CWS
BSEN
SHADOW
LUMA
BORDER
LD1/2
DHOR
ARWDB
VCLK
HORD 5
CH
CHS
VERTD
6
6
LP
NROW
DVERT
4
DADDR
WADDR
DHOR
DVERT
9
5
RAEN,CAEN
ARWDB
DATA
DAEN
RAEN,CAEN
8
2
CHARACTER ROMS
12-BIT SHIFT
REGISTERS
VDD
VSS
VDDA
VSSA
ROUT
GOUT
BOUT
FBKG
HTONE
HFLB
RP
VCO
VFLB
SSB
SCK
SDA
6
8
7
5
2
3
10
2
2
12
6
5
LP
NROW
4
12
9
16
4
1
15
14
13
12
11
MYSON
TECHNOLOGY
MTV004
MTV004 Revision 4.0 06/24/1999
2/9
1.0 CONNECTION DIAGRAM
(16 pins PDIP 300 mil PACKAGE)
VSSA
VCO
RP
VDDA
HFLB
SSB
SDA
SCK
MTV004
VSS
ROUT
GOUT
BOUT
FBKG
HTONE
VFLB
VDD
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
2.0 PIN DESCRIPTIONS
Name
I/O
Pin#
Function
VSSA
-
1
Analog Ground.
VCO
I/O
2
Voltage Control Oscillator. This pin is used to control the internal oscillator
frequency by DC voltage input from an external low pass filter.
RP
I/O
3
Bias Resistor. The bias resistor is used to regulate the bias current for the
internal oscillator to resonate at the specific dot frequency.
VDDA
-
4
Analog Power Supply. Positive 5 V DC supply for internal analog circuitry.
A 0.1uF decoupling capacitor should be connected across to VDDA and
VSSA as close to the device as possible.
HFLB
I
5
Horizontal Input. This pin is used to input the horizontal synchronizing
signal. It is triggered by a negative edge and has an internal pull-up resistor.
SSB
I
6
Serial Interface Enable. Used to enable the serial data and to select I
2
C or
SPI bus operation. If this pin is left floating, the I
2
C bus is enabled, otherwise
the SPI bus is enabled.
SDA
I
7
Serial Data Input. The external data transfers through this pin to the internal
display and control registers. It has an internal pull-up resistor.
SCK
I
8
Serial Clock Input. Clock input pin used to synchronize transferring of data.
It has an internal pull-up resistor.
VDD
-
9
Digital Power Supply. Positive 5 V DC supply for internal digital circuitry. A
0.1uF decoupling capacitor should be connected across to VDD and VSS as
close to the device as possible.
VFLB
I
10
Vertical Input. This pin is used to input the vertical synchronizing signal. It is
negatively triggered and has an internal pull-up resistor.
HTONE
O
11
Half Tone Output. This pin is used to attenuate external R,G,B amplifiers
for a transparent windowing effect.
FBKG
O
12
Fast Blanking Output. Used to cut off external R,G,B signals while
the chip is displaying characters or windows.
BOUT
O
13
Blue Color Output. Blue color video signal output.
GOUT
O
14
Green Color Output. Green color video signal output.
ROUT
O
15
Red Color Output. Red color video signal output.
VSS
-
16
Digital Ground.
MYSON
TECHNOLOGY
MTV004
MTV004 Revision 4.0 06/24/1999
3/9
3.0 FUNCTIONAL DESCRIPTIONS
3.1 Serial Data Interface
The serial data interface receives data transmitted from an external controller. There are 2 types of bus that
can be accessed through the serial data interface: SPI bus and I
2
C bus.
3.1.1 SPI Bus
While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. A valid transmission should
be started by pulling SSB to "low" level, enabling MTV004 in receiving mode, and retaining "low" level until the
last cycle for a complete data packet transfer. The protocol is shown in Figure 2:
Figure 2. Data Transmission Protocol
There are 3 transmission formats as shown below:
Format (a) R - C - D
R - C - D
R - C - D ..........
Format (b) R - C - D
C - D
C - D
C - D .......
Format (c) R - C - D
D
D
D
D
D .........
R=row address, C=column address, D=display data
3.1.2 I
2
C Bus
The I
2
C bus operation is only selected when the SSB pin is left floating. A valid transmission should begin by
writing the slave address 7AH, which is the mask option, to MTV004. The protocol is shown in Figure 3:
SCK
SDA
fist byte
START
ACK
second byte
last byte
ACK
STOP
B7
B6
B0
B7
B0
Figure 3. Data Transmission Protocol (I
2
C)
There are 3 transmission formats as shown below:
Format (a) S - R - C - D
R - C - D
R - C - D ..........
Format (b) S - R - C - D
C - D
C - D
C - D .......
Format (c) S - R - C - D
D
D
D
D
D ........
S=slave address, R=row address, C=column address, D=display data
Each arbitrary length of data packet consists of 3 portions: row address (R), column address (C) and display
data (D). Format (a) is suitable for updating small amounts of data that will be allocated with different row and
column addresses. Format (b) is recommended for updating data that has the same row address but a different
column address. Format (c) should be used for massive data updating or a full-screen data change to increase
MS
B
LSB
SSB
SCK
SDA
first byte
last byte
MYSON
TECHNOLOGY
MTV004
MTV004 Revision 4.0 06/24/1999
4/9
transmission efficiency. Row and column addresses are incremented automatically when format (c) is applied.
Furthermore, the locations in columns 24-29 should be filled with dummy data.

The MSB (b7) bit is used to distinguish row and column addresses when transferring data from the external
controller. The b6 bit is used to differentiate column addresses for formats (a), (b) and (c), respectively. The
address configuration is shown in Table 1.
Table 1. Address Configuration in Interface
Address
b7
b6
b5
b4
b3
b2
b1
b0
Format
Row
1
x
x
x
R3
R2
R1
R0
a,b,c
Columnab
0
0
x
C4
C3
C2
C1
C0
a,b
Columnc
0
1
x
C4
C3
C2
C1
C0
c
The data transmission is permitted to change from format (a) to formats (b) and (c), or from format (b) to format
(a), but not from format (c) back to formats (a) and (b). The alternation between formats is configured according
to the state diagram shown in Figure 4.
Initiate
ROW
COL
c
COL
ab
DA
c
DA
ab
1, X
0, 1
0, 0
X, X
X, X
0, 1
1, X
1, X
format (a)
format (b)
format (c)
X, X
0, X
Input = b7, b6
0, 0
Figure 4. Format State Diagram
3.2 Address Bus Administrator
The administrator manages bus address arbitration of display registers (RAM) during external data writing or
internal display control. The external data writing through the serial data interface to RAM must be
synchronized by internal display timing. In addition, the administrator also provides automatic incrementing to
the address bus when external writing using format (c) and the full-screen display control are applied.
3.3 Vertical Control Logic
The vertical logic generates different vertical display sizes for most display standards in current monitors. The
vertical display size is calculated using the information of the double character height bit (CHS) and vertical
display height control registers (CH5-CH0). The algorithm of the repeating character line display is shown in
Tables 2 and 3. The programmable vertical size range is 160 lines to maximum 1260 lines.
MYSON
TECHNOLOGY
MTV004
MTV004 Revision 4.0 06/24/1999
5/9
The vertical display center for a full-screen display may be figured out according to the information of the
vertical starting position register (VERTD) and VFLB input. The vertical delay, starting from the falling edge of
VFLB, is calculated using the following equation:
Vertical delay time = (VERTD * 4 + 1) * H
H = 1 horizontal line display time
Table 2. Repeat Line Character Weight
CH5 - CH0
Repeat Line Weight
CH5,CH4=11
(+16)*3
CH5,CH4=10
(+16)*2
CH5,CH4=0x
+16
CH3=1
+8
CH2=1
+4
CH1=1
+2
CH0=1
+1
Table 3. Repeat Line Character Number
Repeat Line #
Repeat Line
Weight
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
+1
-
-
-
-
-
-
-
-
v
-
-
-
-
-
-
-
+2
-
-
-
-
v
-
-
-
-
-
-
-
v
-
-
-
+4
-
-
v
-
-
-
v
-
-
-
v
-
-
-
v
-
+8
-
v
-
v
-
v
-
v
-
v
-
v
-
v
-
v
+16
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Note: " v " means the nth line in the character would be repeated once, while "-" means the nth line in the
character would not be repeated.
3.4 Horizontal Control Logic
The horizontal control logic is used to generate control timing for the horizontal display based on the double
character width bit (CWS), horizontal positioning register (HORD) and HFLB input. A horizontal display line
consists of 384 dots, which include 288 dots for 24 display characters and 96 dots for the remaining blank
region. The horizontal delay starting from the HFLB falling edge is calculated using the following equation:
horizontal delay time = (HORD * 6 + 61)* P - phase error detection pulse width
P= 1 pixel display time = 1 horizontal display time / 384
3.5 Phase Lock Loop (PLL)
On-chip PLL generates system clock timing (VCLK) by tracking the input HFLB. The frequency of VCLK is
determined using the following equation:
VCLK = HFLB Freq.* 384 ,
The frequency ranges from 3.84MHz to 38.4MHz. See Table 4.
Table 4. Frequency Range
HFLB
VCLK
10KHz to 100KHz
3.84MHz to 38.4MHz
© 2018 • ChipFind
Контакты
Главная страница