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Datasheet: MTD508 (Myson Technology)

8-port Switch

 

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8-Port 10M/100M Ethernet Switch
MTD508
BLOCK DIAGRAM
GENERAL DESCRIPTION
FEATURES
Myson-Century Technology
USA:
4020 Moorpark Avenue Suite 115
San Jose, CA, 95117
Tel: 408-243-8388 Fax: 408-243-3188
Sales@myson.com.tw
www.myson.com.tw
www.century-semi.com
Rev.1.3 December 2001
page 1 of 19
Myson-Century Technology, Inc.
Taiwan:
No. 2, Industry East Rd. III,
Science-Based Industrial Park, Hsin-Chu, Taiwan
Tel: 886-3-5784866 Fax: 886-3-5784349
The MTD508 complies fully with the IEEE802.3,
802.3u and 802.3x specifications and is a non-
blocking 8-port 10M/100M Ethernet switch device.
The MTD508 supports 8 RMII ports for 10M/100M
operations. 1MBytes/2MBytes memory interface
provides maximum 1365 packet buffers for Ethernet
packet buffering. Up to 8192 address entries are
provided by the MTD508, and the MTD508 uses full
Ethernet address to compare algorithm for
minimizing hashing collision events.
The MTD508 provides EEPROM interface to
configure port trunking, port VLAN, static entry,
802.3x flow control threshold, flooding port,
broadcast control threshold. Each MTD508 port
supports 10M/100M auto-negotiation by MDC/MDIO
interface for connecting external PHY devices.
The MTD508 also provides 10 pins for Link/RX
activities, packet butter utilization LED display
functoin.
IEEE802.3 and IEEE802.3u compliant.
Provides 8 RMII (Reduced Media Independent
Interface) ports.
Programmable 1K/8K MAC addresses filtering.
Store and forward switching function and bad
packet filtering function.
Optional back-pressure/802.3x flow control/
flooding control/broadcast control.
Optional EEPROM interface for advanced switch
configurations.
1MB/2MB SGRAM/SDRAM flexible memory
interface.
Port VLAN/trunking.
Link/Rx activities, packet buffer utilization LED
display.
75MHz for non-blocking for 8-port switch
operation.
Built-in interna/external memory test function.
160-pin PQFP package, 3.3V operating voltage.
SDRAM/
SGRAM
Interface
Memory
Controller
Memory
Port
Switch
Logic
DMA0
DMA1
DMA2
DMA3
DMA4
MAC0
MAC1
MAC2
MAC3
MAC4
RMII5
RMII3
RMII2
RMII1
RMII0
Arbiter
DMA6
DMA7
MAC5
MAC7
RMI7
RMII6
DMA5
MAC6
RMII4
MTD508
page 2 of 19
Myson-Century Technology
SYSTEM DIAGRAM
SGRAM
(256k32x1)
SGRAM
(512k32x1)
SDRAM
(256k32x2)
(**Programmable)
(**Optional)
EEPROM
MTD508
LEDs
RMII0-3
RMII4-7
QUAD
PHYsceiver
QUAD
Transformer
RJ45
MII management
QUAD
PHYsceiver
QUAD
Transformer
RJ45
MTD508
page 3 of 19
Myson-Century Technology
PIN CONNECTION
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
12
0
11
9
11
8
11
7
11
6
11
5
11
4
11
3
11
2
111
11
0
10
9
10
8
10
7
10
6
10
5
10
4
10
3
10
2
10
1
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
CR
S
V
D
2
T
X
D
2_1
T
X
D
2_0
TX
EN
2
GNDO
VCCO
R
X
D
2_0
R
X
D
2_1
CR
S
D
V
3
T
X
D
3_1
T
X
D
3_0
TX
EN
3
R
X
D
3_0
R
X
D
3_1
CR
S
D
V
4
COL
4
T
X
D
4_3
T
X
D
4_2
T
X
D
4_1
T
X
D
4_0
TX
EN
4
TX
C
4
RXC4
RX
DV4
GNDI
V
CCI
R
X
D
4_0
R
X
D
4_1
R
X
D
4_2
R
X
D
4_3
CR
S
D
V
5
T
X
D
5_1
T
X
D
5_0
TX
EN
5
R
X
D
5_0
R
X
D
5_1
CR
S
D
V
6
T
X
D
6_1
T
X
D
6_0
TX
EN
6
L
E
DCL
K1
DQ0
DQ1
VC
C
I
GNDI
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VC
C
O
GNDO
DQ1
6
DQ1
7
DQ1
8
DQ1
9
VC
C
I
GNDI
DQ2
0
VC
C
O
GNDO
DQ2
1
DQ2
2
DQ2
3
WE
B
CA
SB
RA
SB
CS
0
B
BA
VC
C
I
GNDI
CS
1
B
AD
0
AD
1
AD
2
VC
C
I
GNDI
AD
3
AD
4
LEDCLK2
GNDO
VCCO
LEDDATA7
LEDDATA6
LEDDATA5
LEDDATA4
LEDDATA3
LEDDATA2
LEDDATA1
LEDDATA0
GNDI
CLK25M
VCCI
SDC
SDIO
EECLK
EEDATA
RESETB
GNDO
REFCLK
VCCO
MDIO
MDC
GNDI
VCCI
CRSDV0
TXD0_1
TXD0_0
TXEN0
GNDI
VCCI
RXD0_0
RXD0_1
CRSDV1
TXD1_1
TXD1_0
TXEN1
RXD1_0
RXD1_1
VCCO
GNDO
AD5
AD6
AD7
AD8
VCCI
MEMCLK
GNDI
DO8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ24
DQ25
DQ26
VCCO
GNDO
DO27
DO28
DO29
DO30
DO31
VCCI
SYSCLK
GNDI
RXD7_1
RXD7_0
VCCI
GDNI
TXEN7
TXD7_0
TXD7_1
CRSDV7
RXD6_1
RXD6_0
MTD508
160-pin PQFP
MTD508
page 4 of 19
Myson-Century Technology
PIN DESCRIPTION
RMII/MII Port Interface Pins
Name
I/O
Pin
Description
CRSDV0
I
147
Port0 RMII receive interface signal, CRSDV0 is asserted high when port0
media is non-idle.
RXD0_0
I
153
Port0 RMII receive data bit0.
RXD0_1
I
154
Port0 RMII receive data bit1.
TXEN0
O
150
Port0 RMII transmit enable signal.
TXD0_0
O
149
Port0 RMII transmit data bit0.
TXD0_1
O
148
Port0 RMII transmit data bit1.
CRSDV1
I
155
Port1 RMII receive interface signal, CRSDV1 is asserted high when port1
media is non-idle.
RXD1_0
I
159
Port1 RMII receive data bit0.
RXD1_1
I
160
Port1 RMII receive data bit1.
TXEN1
O
158
Port1 RMII transmit enable signal.
TXD1_0
O
157
Port1 RMII transmit data bit0.
TXD1_1
O
156
Port1 RMII transmit data bit1.
CRSDV2
I
1
Port2 RMII receive interface signal, CRSDV2 is asserted high when port2
media is non-idle.
RXD2_0
I
7
Port2 RMII receive data bit0.
RXD2_1
I
8
Port2 RMII receive data bit1.
TXEN_2
O
4
Port2 RMII transmit enable signal.
TXD2_0
O
3
Port2 RMII transmit data bit0.
TXD2_1
O
2
Port2 RMII transmit data bit1.
CRSDV3
I
9
Port3 RMII receive interface signal, CRSDV3 is asserted high when port3
media is non-idle.
RXD3_0
I
13
Port3 RMII receive data bit0.
RXD3_1
I
14
Port3 RMII receive data bit1.
TXEN3
O
12
Port3 RMII transmit enable signal.
TXD3_0
O
11
Port3 RMII transmit data bit0.
TXD3_1
O
10
Port3 RMII transmit data bit1.
CRSDV4
I
15
Port4 RMII receive interface signal, CRSDV2 is asserted high when port4
media is non-idle.
RXDV4
I
24
Port4 MII receive data valid. In RMII mode, this pin is not used.
RXCLK4
I
23
Port4 MII receive clock signal. In RMII mode, this pin is not used.
RXD4_3
I
30
Port MII receive data bit3. In RMII mode, this pin is not used.
RXD4_2
I
29
Port MII receive data bit2. In RMII mode, this pin is not used.
RXD4_0
I
27
Port MII receive data bit0.
RXD4_1
I
28
Port MII receive data bit1.
TXEN4
O
21
Port4 RMII transmit enable signal.
MTD508
page 5 of 19
Myson-Century Technology
TXCLK4
I
22
Port4 RMII transmit clock signal. In RMII mode, this pin is not used.
TXD4_3
O
17
Port4 MII transmit data bit3. In RMII mode, this pin is not used.
TXD4_2
O
18
Port4 MII transmit data bit2. In RMII mode, this pin is not used.
TXD4_0
O
20
Port4 RMII/MII transmit data bit0.
TXD4_1
O
19
Port4 RMII/MII transmit data bit1.
COL4
I
16
Port4 MII collision input. In RMII mode, this pin is not used.
CLK25M
O
155
Port4 MII 25MHz clock output.
CRSDV5
I
31
Port5 RMII receive interface signal, CRSDV5 is asserted high when port5
media is non-idle.
RXD5_0
I
35
Port5 RMII receive data bit0.
RXD5_1
I
36
Port5 RMII received data bit1.
TXEN5
O
34
Port5 RMII transmit enable signal.
TXD5_0
O
33
Port5 RMII transmit data bit0.
TXD5_1
O
32
Port5 RMII transmit data bit1.
CRSDV6
I
37
Port6 RMII receive interface signal, CRSDV6 is asserted high when port5
media is non-idle.
RXD6_0
I
41
Port6 RMII receive data bit0.
RXD6_1
I
42
Port6 RMII received data bit1.
TXEN6
O
40
Port6 RMII transmit enable signal.
TXD6_0
O
39
Port6 RMII transmit data bit0.
TXD6_1
O
38
Port6 RMII transmit data bit1.
CRSDV7
I
43
Port7 RMII receive interface signal, CRSDV7 is asserted high when port5
media is non-idle.
RXD7_0
I
39
Port7 RMII receive data bit0.
RXD7_1
I
50
Port7 RMII received data bit1.
TXEN7
O
46
Port7 RMII transmit enable signal.
TXD7_0
O
45
Port7 RMII transmit data bit0.
TXD7_1
O
44
Port7 RMII transmit data bit1.
SGRAM/SDRAM Interface Pins
Name
I/O
Pin
Description
AD[8:0]
O
75-78, 81-82,
85-87
Memory row/column address bus outputs.
AD[7:0] are row/column address[7:0].
AD[8]: This pin should connect to SGRAM/SDRAM MSB address bit.
DQ[31:0]
I/O
54-58, 61-71,
96-98, 101,
104-107, 110-
115, 118-119
Memory data bus.
RASB
O
93
SGRAM/SDRAM row address select.
RMII/MII Port Interface Pins
Name
I/O
Pin
Description
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