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Datasheet: CS6710 (Myson Technology)

155Mbps Fiber Optic Pin Pre-amplifier With Agc

 

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BLOCK DIAGRAM
GENERAL DESCRIPTION
FEATURES
CS6710
155Mbps Fiber-Optic PIN Pre-Amplifier with AGC
USA:
4020 Moorpark Avenue Suite 115
San Jose, CA, 95115
Tel: 408-243-8388 Fax: 408-243-3188
Sales@myson.com.tw
www.myson.com.tw
Rev. 1.2 November 2002
page 1 of 12
Myson Century, Inc.
Taiwan:
No. 2, Industry East Rd. III,
Science-Based Industrial Park, Hsin-Chu, Taiwan
Tel: 886-3-5784866 Fax: 886-3-5784349
The CS6710 is a transimpedance amplifier with
AGC for 155Mbps fiber channel applications. The
AGC function allows -39dB to +3dB input dynamic
range, thus providing a low cost solution to longer-
reach ATM systems.
The CS6710 is fabricated in a standard CMOS
process and provided in die form to be assembled
with a photodiode into a metal can.
3.3V or 5V operation.
100
to 55k
single-ended transimpedance gain
with 50
termination.
Minimal 95MHz bandwidth at maximum gain.
On-chip Automatic Gain Control (AGC).
Differential outputs drive a high impedance load.
Available in die form.
Typical input saturation current of 4.5mA.
Figure-1
V
CC
GND
PADOUTP
PADPINA
PADPINK
PADOUTN
CS6710
GND
470pF
Fiber channel
SDH/SONET
Ethernet
APPLICATIONS
CS6710
page 2 of 12
DIE CONNECTION DIAGRAM
Figure-2
Bare Die Information
Note: The coordinates start from the center of the die to the center of the pad, and the total die size does not include seal
ring and scribe line.
Pad No. Description
X (



m)
Y (



m)
1
GND
-352.00
261.70
2
PADOUTP
-352.00
111.70
3
V
CC
-352.00
-261.70
4
PADPINK
-135.95
-352.00
5
PADPINA
153.95
-360.00
6
VH
352.00
-361.95
7
V
CC
352.00
-261.70
8
PADOUTN
352.00
111.70
9
GND
352.00
261.70
1
2
3
4
7
8
9
GND
GND
PADOUTP
V
CC
V
CC
PADOUTN
PADPINK
PADPINA
803.0
m
900.5
m
5
X
Y
6
VH
CS6710
page 3 of 12
Area A: total chip size in Figure 2 mentioned 803*900.5 um.
Area B: seal ring, 20um/side
Area C: scribe line residue after die saw,
X=17.5
2.5 um/side, Y=17.5
2.5um/side
Actual size after die-saw,
Max: 883*980.5um, Min: 873*970.5um
Chip thinkness: 10mil
1mil
CS6710
Chip
A
B
C
CS6710
page 4 of 12
PIN DESCRIPTION
Pin Name
Pin No.
Description
GND
1,9
Ground pin. Connect to the most negative supply voltage.
PADOUTP
2
Differential data output pin. This pin goes high when current flows into pin PADPINA.
V
CC
3,7
Power pin. Connect to the most positive supply voltage.
PADPINK
4
Connect to the cathode of the photodiode.
PADPINA
5
Input pin. Connect to the anode of the photodiode.
PADOUTN
8
Differential data output pin. Complementary to pin PADOUTP.
VH
6
Test pin. Measure the voltage of this pin can get the transimpedance gain. Leave this pin open in
typical application circuits.
CS6710
page 5 of 12
FUNCTIONAL DESCRIPTION
The CS6710 is a transimpedance pre-amplifier fabricated in a CMOS process. The CS6710 consists of a
transimpedance amplifier, an AGC control block, an output buffer, and a voltage regulator.
Transimpedance Amplifier
The transimpedance amplifier in CS6710 is a high gain, single ended amplifier with a feedback resistor. The
minimum differential output swing is 20mV with high impedance load at -39dBm input. The feedback resistor
converts the input current to voltage at the output node.
AGC Control Block
The AGC control block changes the feedback resistance in the CS6710 by using a voltage controlled MOS
transistor. The AGC control block starts working when the input signal is larger than 1.8
A (-30dBm at 0.9 A/W).
Output Buffer
The output of the single-ended amplifier becomes differential signal after going through the output buffer. The
output is able to drive a load larger than 500
.
Voltage Regulator
In order to minimize the influence of power supply on noise performance, a voltage regulator is incorporated in
the CS6710. Moreover, the external capacitor also reduces the power supply noise at high frequencies.
FUNCTIONAL DIAGRAM
Figure-3
AGC
TIA
BG
REG
BIAS
R
PADOUTP
PADOUTN
PADPINA
PADPINK
CS6710
page 6 of 12
TYPICAL OPERATING CURVE
(Ta=25
C, C
IN
=1pF, data is collected by single-ended output with 50ohm termination).
Gain vs Input
0
10
20
30
40
50
60
70
-40
-30
-20
-10
0
Input (dBm)
Gain (Kohm)
Output vs Input
0
20
40
60
80
100
120
140
160
-40
-30
-20
-10
0
Input (dBm)
Output (mV)
CS6710
page 7 of 12
Output vs Frequency
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
1.E+07
1.E+08
1.E+09
Frequency (Hz)
Output (dBm)
-10dBm
-15dBm
-20dBm
-25dBm
-30dBm
-35dBm
Icc vs Vcc
20
21
22
23
24
25
26
27
3
3.5
4
4.5
5
5.5
Vcc (V)
Icc (mA)
CS6710
page 8 of 12
EYE DIAGRAMS
Input 1uA@3.3V
Input 1uA@5V
Input 100uA@3.3V
Input 100uA@5V
CS6710
page 9 of 12
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS (DC)
Symbol
Parameter
Rating
Unit
V
CC
Power supply
6
V
T
a
Operating ambient temperature range
-40 to +85
C
T
STG
Storage temperature range
-65 to +150
C
Symbol
Parameter
Rating
Unit
V
CC
Power supply range
3.0 to 5.5
V
T
a
Ambient temperature range
-40 to +85
C
C
IN
Total capacitance at the PADPINA pin
0.7 to 1.0
pF
Symbol
Parameter
Min
Typ
Max
Unit
I
CC
Supply current
-
22 (3.3V)
24 (5V)
32 (3.3V)
34 (5V)
mA
V
b
PIN bias voltage (PINK-PINA)
1.5
1.65
1.8
V
V
cm
Common mode output voltage
-
Vcc-2.3 (3.3V)
Vcc-2.5 (5V)
-
V
R
out
Output impedance (single end)
-
50
-
CS6710
page 10 of 12
ELECTRICAL CHARACTERISTICS (AC)
Note 1.With PIN responsivity of 0.9A/W, extinction ratio of 10dB, and BER of 10E-10
Note 2.With -39dBm input, 0.9A/W, and C
IN
=1.0pF
Note 3.Output with 50ohm termination
Symbol
Parameter
Min
Typ
Max
Unit
I
n
Input RMS noise, DC to 100MHz
-
7.5
8.5
nA
PIN,min
Optical sensitivity (note 1)
-
-39
-
dBm
PIN,max
Optical saturation (note 1)
-
3
-
dBm
I
in
, max
Maximum input current (note 1)
3.0
4.5
-
mA
Transimpedance gain@1MHz (note 3)
Gain
(single-ended)
100
-
55k
(differential)
200
-
110k
BW
Bandwidth (-3dB) (Note 2)
95
-
-
MHz
T
r
,T
f
Output rise / fall times (20%-80%)
-
-
2.2
ns
T
pwd
Pulse width distortion
-
-
10
%
OS
Overshoot
-
-
10
%
dVout
Differential output voltage (note 3)
-
-
700
mV
T
agc
AGC converging time
-
-
0.7
ms
PSRR
Power supply rejection ratio
35
-
-
dB
CS6710
page 11 of 12
TYPICAL APPLICATION CIRCUIT
Post-Amp
9
CS6702
8
7
GND
VCC
6
5
CS6710
4
3
VH
PIN
PADPINA
C1
0.1uF
PADPINK
GND
PADOUTN
C5
1nF
Vcc
C4
0.1uF
PADOUTP
Vcc
C3
0.1uF
DINN
2
1
GND
DINP
C2
470pF
GND
GND
DINP
8
CS6702
PADPINK
C2
470pF
C5
1nF
VH
C4
0.1uF
C1
0.1uF
Vcc
5
1
Post-Amp
C3
0.1uF
PADOUTP
GND
GND
CS6710
2
GND
PADPINA
4
GND
VCC
3
GND
Vcc
9
DINN
C14
1nF
GND
PIN
VCC
PADOUTN
7
6
CASE IS GROUND
PHOTODIODE
TOP VIEW OF TO-46 HEADER
Vcc
DOUTN
CS6710
470pF
DOUTP
GND
CASE IS GROUND
PHOTODIODE
TOP VIEW OF TO-46 HEADER
Vcc
DOUTN
CS6710
470pF
DOUTP
GND
Figure-6 Typical TO-CAN Assembly
Figure-4
Figure-5
CS6710
page 12 of 12
APPLICATION INFORMATION
Typical application circuit is shown in Figure4. An alternative connection of the PIN diode is to connect the
cathode of the PIN diode to VCC with a decoupling capacitor to ground. This configuration requires one more
capacitor connected from PADPINK pin to ground, as shown in Figure5.
LAYOUT CONSIDERATIONS
Noise performance is directly proportional to the total capacitance at the PADDINA pin. Minimise the bond-wire
length, and the capacitance of the PIN diode. Figure6 showns the typical layout of TO-CAN.
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