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Datasheet: CS5864 (Myson Technology)

TFT Source Driver With Timing Controller (288 Outputs)

 

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BLOCK DIAGRAM
GENERAL DESCRIPTION
FEATURES
CS5864
TFT Source Driver With Timing Controller (288 Outputs)
Sales@myson.com.tw
www.myson.com.tw
Rev. 1.0 August 2003
page 1 of 39
Myson Century, Inc.
No. 2, Industry East Rd. III,
Science-Based Industrial Park, Hsin-Chu, Taiwan
Tel: 886-3-578-4866 Fax: 886-3-578-4349
The CS5864 is a data driver IC with timing
controller for color TFT LCD panel. It provides
selectable 288 or 240 output channels for
application. For lower power dissipation, the circuit
architecture with a special method is designed, and
line inversion is suggested on applications. The
CS5864 can select dithering technique function to
obtain 8-bit resolution. For better performance, a
wide range supply voltage and small output deviation
are designed in this chip. This chip also supplies 9
sections of voltage-reference for gamma correction
and the power dissipation on the gamma correction
resistors is also concerned, thereby making this chip
more suitable for small size color TFT panels.
Specially designed for small size panel color TFT
LCD driver with timing controller
Output: 288 or 240 output channels
8-bit resolution, 256 gray-scale with dithering
Power for LCD driving: 3.0 ~ 4.5V
Power for digital interface: 2.5 ~ 3.6V
Power for level shift circuit: 4.0 ~ 6.0V
Max operating frequency: 27 MHz
Output dynamic range: 0.1 ~ AVDD-0.1V
Output deviation: 20mV
Output setting time: 10~12uS
Cascade function with bi-directional shift control
With DC to DC control circuit for back-light power
With level shift circuit for Vcom swing
V1 ~ V9 for adjusting gamma correction
COG package
Line inversion
With standby mode
9 timings support
DIN[7:0]
MASL
Hsync
Vsync
TEST0/1
DataPath
Pre-filtering
Dithering
Data Alignment
clk_gen
timing_gen
DCLK
PFON
DITH
SWD
STB
PS
SHDB
SEL 0/1/2/3
SHL
RSTB
UD
FPOL
AVD
D1
AGN
D
1
FRP
FB
DRV
PO
L
DI
O2
DI
O1
UDV
STV1 STV2
OEV
CKV
O
u
t[1
]
Ou
t[2
8
8
]
SHT6
DDX[1-6]
s2p
LCKDLK
STHR/L
DDX[1-18]
dclk_o
DDX_CLK
DC/DC off
pwdown
LD
FRM
POL_s
Slave_ctrl
FRPin
Level shift
Circuit
D/D converter
Control Circuit
CHNSL
Shift Control Register
Data Register
Latch
D/A Switch
Output Buffer
VSET
V1-V9
Q1
H
*This datasheet, which contains proprietary and trade secret information of MYSON CENTURY, INC., is confidential and
subject to various privileges against unauthorized disclosure.
© 2018 • ChipFind
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