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Datasheet: Y100N10E (Motorola, Inc.)

Tmos Power Fet 100 Amperes 100 Volts Rds(on) = 0.011 Ohm

 

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Motorola, Inc.
1
Motorola TMOS Power MOSFET Transistor Device Data
Designer's
TM
Data Sheet
TMOS E-FET
.
TM
Power Field Effect Transistor
NChannel EnhancementMode Silicon Gate
This advanced TMOS power FET is designed to withstand high
energy in the avalanche and commutation modes. This new energy
efficient design also offers a draintosource diode with fast
recovery time. Designed for high voltage, high speed switching
applications in power supplies, converters, PWM motor controls,
and other inductive loads. The avalanche energy capability is
specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.
Avalanche Energy Specified
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS
(TC = 25
C unless otherwise noted)
Rating
Symbol
Value
Unit
DrainSource Voltage
VDSS
100
Vdc
DrainGate Voltage (RGS = 1 M
)
VDGR
100
Vdc
GateSource Voltage -- Continuous
GateSource Voltage
-- NonRepetitive (tp
10 ms)
VGS
VGSM
20
40
Vdc
Vpk
Drain Current -- Continuous @ TC = 25
C
Drain Current
-- Single Pulse (tp
10
s)
ID
IDM
100
300
Adc
Apk
Total Power Dissipation
Derate above 25
C
PD
300
2.38
Watts
W/
C
Operating and Storage Temperature Range
TJ, Tstg
55 to 150
C
Single Pulse DraintoSource Avalanche Energy -- Starting TJ = 25
C
(VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 100 Apk, L = 0.1 mH, RG = 25
)
EAS
250
mJ
Thermal Resistance -- Junction to Case
Thermal Resistance
-- Junction to Ambient
R
JC
R
JA
0.42
40
C/W
Maximum Lead Temperature for Soldering Purposes, 1/8
from case for 10 seconds
TL
260
C
Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.
EFET and Designer's are trademarks of Motorola, Inc.
TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
Order this document
by MTY100N10E/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MTY100N10E
TMOS POWER FET
100 AMPERES
100 VOLTS
RDS(on) = 0.011 OHM
CASE 340G02, STYLE 1
TO264
Motorola Preferred Device
D
S
G
Motorola, Inc. 1995
MTY100N10E
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(TJ = 25
C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0, ID = 250
A)
Temperature Coefficient (Positive)
V(BR)DSS
100
--
--
115
--
--
Vdc
mV/
C
Zero Gate Voltage Drain Current
(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125
C)
IDSS
--
--
--
--
10
200
Adc
GateBody Leakage Current (VGS =
20 Vdc, VDS = 0)
IGSS
--
--
100
nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250
Adc)
Threshold Temperature Coefficient (Negative)
VGS(th)
2.0
--
--
7
4
--
Vdc
mV/
C
Static DrainSource OnResistance (VGS = 10 Vdc, ID = 50 Adc)
RDS(on)
--
--
0.011
Ohm
DrainSource OnVoltage (VGS = 10 Vdc)
(ID = 100 Adc)
(ID = 50 Adc, TJ = 125
C)
VDS(on)
--
--
1.0
--
1.2
1.0
Vdc
Forward Transconductance (VDS = 6 Vdc, ID = 50 Adc)
gFS
30
49
--
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1 MHz)
Ciss
--
7600
10640
pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1 MHz)
Coss
--
3300
4620
Reverse Transfer Capacitance
f = 1 MHz)
Crss
--
1200
2400
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
(VDD = 50 Vdc, ID = 100 Adc,
VGS = 10 Vdc,
RG = 9.1
)
td(on)
--
48
96
ns
Rise Time
(VDD = 50 Vdc, ID = 100 Adc,
VGS = 10 Vdc,
RG = 9.1
)
tr
--
490
980
TurnOff Delay Time
VGS = 10 Vdc,
RG = 9.1
)
td(off)
--
186
372
Fall Time
G = 9.1
)
tf
--
384
768
Gate Charge
(See Figure 8)
(VDS = 80 Vdc, ID = 100 Adc,
VGS = 10 Vdc)
QT
--
270
378
nC
(See Figure 8)
(VDS = 80 Vdc, ID = 100 Adc,
VGS = 10 Vdc)
Q1
--
50
--
(VDS = 80 Vdc, ID = 100 Adc,
VGS = 10 Vdc)
Q2
--
150
--
Q3
--
118
--
SOURCEDRAIN DIODE CHARACTERISTICS
Forward OnVoltage
(IS = 100 Adc, VGS = 0 Vdc)
(IS = 100 Adc, VGS = 0 Vdc, TJ = 125
C)
VSD
--
--
1
0.9
1.2
--
Vdc
Reverse Recovery Time
(See Figure 14)
(IS = 100 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/
s)
trr
--
145
--
ns
(See Figure 14)
(IS = 100 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/
s)
ta
--
90
--
(IS = 100 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/
s)
tb
--
55
--
Reverse Recovery Stored Charge
QRR
--
2.34
--
C
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25
from package to center of die)
LD
--
4.5
--
nH
Internal Source Inductance
(Measured from the source lead 0.25
from package to source bond pad)
LS
--
13
--
nH
(1) Pulse Test: Pulse Width
300
s, Duty Cycle
2%.
(2) Switching characteristics are independent of operating junction temperature.
MTY100N10E
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
R
DS(on)
, DRAINT
OSOURCE RESIST
ANCE
(NORMALIZED)
R
DS(on)
, DRAINT
OSOURCE RESIST
ANCE (OHMS)
R
DS(on)
, DRAINT
OSOURCE RESIST
ANCE (OHMS)
1000000
100000
1000
100
1
0
40
80
100
120
1.8
1.6
1.4
1.2
0.8
0.6
50
25
0
25
50
75
100
125
150
0.011
0.0105
0.01
0.0095
0.009
0.008
ID, DRAIN CURRENT (AMPS)
15 V
0.018
0.016
0.014
0.012
0.006
0
100
200
25
C
150
50
200
0
0
2
4
6
8
10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
Figure 1. OnRegion Characteristics
I D
, DRAIN CURRENT
(AMPS)
I D
, DRAIN CURRENT
(AMPS)
VGS, GATETOSOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
ID, DRAIN CURRENT (AMPS)
Figure 3. OnResistance versus Drain Current
and Temperature
Figure 4. OnResistance versus Drain Current
and Gate Voltage
TJ, JUNCTION TEMPERATURE (
C)
Figure 5. OnResistance Variation with
Temperature
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
Figure 6. DrainToSource Leakage
Current versus Voltage
I DSS
, LEAKAGE (nA)
0
VGS = 10 V
VDS
10 V
VGS = 10 V
TJ = 100
C
55
C
VGS = 10 V
VGS = 0 V
160
120
120
80
60
2
3
4
5
6
10
0
100
200
150
50
TJ = 125
C
0.01
0.008
20
100
40
20
7
8
9
0.0085
1
10
60
TJ = 25
C
80
40
9 V
8 V
7 V
6 V
5 V
TJ = 25
C
100
C
25
C
TJ = 55
C
25
C
100
C
VGS = 10 V
ID = 50 A
MTY100N10E
4
Motorola TMOS Power MOSFET Transistor Device Data
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (
t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when cal-
culating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
24000
20000
16000
12000
8000
4000
0
10
5
0
5
10
15
20
25
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)
C, CAP
ACIT
ANCE (pF)
Figure 7. Capacitance Variation
VGS
VDS
VGS = 0 V
VDS = 0 V
TJ = 25
C
Ciss
Crss
Ciss
Coss
Crss
MTY100N10E
5
Motorola TMOS Power MOSFET Transistor Device Data
V
DS
, DRAINT
OSOURCE VOL
T
AGE (VOL
TS)
V
GS
, GA
TET
OSOURCE VOL
T
AGE (VOL
TS)
100
0
0.5
0.6
0.7
0.8
VGS = 0 V
TJ = 25
C
10000
1000
10
1
10
100
12
10
8
6
4
2
0
0
50
100
150
200
300
Qg, TOTAL GATE CHARGE (nC)
Q2
120
100
80
60
40
20
0
DRAINTOSOURCE DIODE CHARACTERISTICS
VSD, SOURCETODRAIN VOLTAGE (VOLTS)
Figure 8. Gate Charge versus GatetoSource Voltage
I S
, SOURCE CURRENT
(AMPS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
RG, GATE RESISTANCE (OHMS)
t,
TIME (ns)
Figure 10. Diode Forward Voltage versus Current
QT
TJ = 25
C
ID = 100 A
VDD = 50 V
ID = 100 A
VGS = 10 V
TJ = 25
C
td(on)
td(off)
tf
tr
0.9
100
250
80
60
40
20
1.1
1
Q1
Q3
VGS
VDS
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25
C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, "Transient Thermal ResistanceGeneral
Data and Its Use."
Switching between the offstate and the onstate may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10
s. In addition the total power aver-
aged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(R
JC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con-
stant. The energy rating decreases nonlinearly with an in-
crease of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
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