**NChannel EnhancementMode Silicon Gate**

efficient design also offers a draintosource diode with fast

recovery time. Designed for high voltage, high speed switching

applications in power supplies, converters, PWM motor controls,

and other inductive loads. The avalanche energy capability is

specified to eliminate the guesswork in designs where inductive

loads are switched and offer additional safety margin against

unexpected voltage transients.

**MAXIMUM RATINGS**

**Rating**

**Symbol**

**Value**

**Unit**

Vpk

300

Apk

**Designer's Data for "Worst Case" Conditions**-- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit

curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.

TMOS is a registered trademark of Motorola, Inc.

**Preferred**devices are Motorola recommended choices for future use and best overall value.

**REV 2**

**Order this document**

**by MTY100N10E/D**

**SEMICONDUCTOR TECHNICAL DATA**

**TMOS POWER FET**

**100 AMPERES**

**100 VOLTS**

**RDS(on) = 0.011 OHM**

**CASE 340G02, STYLE 1**

**TO264**

**Motorola Preferred Device**

**ELECTRICAL CHARACTERISTICS**

**Characteristic**

**Symbol**

**Min**

**Typ**

**Max**

**Unit**

**OFF CHARACTERISTICS**

--

(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125

--

--

**ON CHARACTERISTICS (1)**

(ID = 50 Adc, TJ = 125

--

1.0

**DYNAMIC CHARACTERISTICS**

**SWITCHING CHARACTERISTICS (2)**

**SOURCEDRAIN DIODE CHARACTERISTICS**

--

**INTERNAL PACKAGE INDUCTANCE**

**TYPICAL ELECTRICAL CHARACTERISTICS**

**Figure 1. OnRegion Characteristics**

**Figure 2. Transfer Characteristics**

**Figure 3. OnResistance versus Drain Current**

**and Temperature**

**Figure 4. OnResistance versus Drain Current**

**and Gate Voltage**

**Figure 5. OnResistance Variation with**

**Temperature**

**Figure 6. DrainToSource Leakage**

**Current versus Voltage**

ID = 50 A

**POWER MOSFET SWITCHING**

The lengths of various switching intervals (

by current from the generator.

ing rise and fall because draingate capacitance varies

greatly with applied voltage. Accordingly, gate charge data is

used. In most cases, a satisfactory estimate of average input

current (IG(AV)) can be made from a rudimentary analysis of

the drive circuit so that

During the rise and fall time interval when switching a resis-

tive load, VGS remains virtually constant at a level known as

the plateau voltage, VSGP. Therefore, rise and fall times may

be approximated by the following:

tf = Q2 x RG/VGSP

where

RG = the gate drive resistance

and Q2 and VGSP are read from the gate charge curve.

During the turnon and turnoff delay times, gate current is

not constant. The simplest calculation uses appropriate val-

ues from the capacitance curves in a standard equation for

voltage change in an RC network. The equations are:

td(off) = RG Ciss In (VGG/VGSP)

a voltage corresponding to the offstate condition when cal-

culating td(on) and is read at a voltage corresponding to the

onstate when calculating td(off).

lead, inside the package and in the circuit wiring which is

common to both the drain and gate current paths, produces a

voltage at the source which reduces the gate drive current.

The voltage is determined by Ldi/dt, but since di/dt is a func-

tion of drain current, the mathematical solution is complex.

The MOSFET output capacitance also complicates the

mathematics. And finally, MOSFETs have finite internal gate

resistance which effectively adds to the resistance of the

driving source, but the internal resistance is difficult to mea-

sure and, consequently, is not specified.

affected by the parasitic circuit elements. If the parasitics

were not present, the slope of the curves would maintain a

value of unity regardless of the switching speed. The circuit

used to obtain the data is constructed to minimize common

inductance in the drain and gate circuit loops and is believed

readily achievable with board mounted components. Most

power electronic loads are inductive; the data in the figure is

taken with a resistive load, which approximates an optimally

snubbed inductive load. Power MOSFETs may be safely op-

erated into an inductive load; however, snubbing reduces

switching losses.

**Figure 7. Capacitance Variation**

AGE (VOL

AGE (VOL

TJ = 25

**DRAINTOSOURCE DIODE CHARACTERISTICS**

**Figure 8. Gate Charge versus GatetoSource Voltage**

**Figure 9. Resistive Switching Time**

**Variation versus Gate Resistance**

**Figure 10. Diode Forward Voltage versus Current**

ID = 100 A

VGS = 10 V

TJ = 25

**SAFE OPERATING AREA**

drain current that a transistor can handle safely when it is for-

ward biased. Curves are based upon maximum peak junc-

tion temperature and a case temperature (TC) of 25

thermal response data in conjunction with the procedures

discussed in AN569, "Transient Thermal ResistanceGeneral

Data and Its Use."

nor rated voltage (VDSS) is exceeded and the transition time

(tr,tf) do not exceed 10

(TJ(MAX) TC)/(R

sipated in the transistor while in avalanche must be less than

the rated limit and adjusted for operating conditions differing

from those specified. Although industry practice is to rate in

terms of energy, avalanche energy capability is not a con-

stant. The energy rating decreases nonlinearly with an in-

crease of peak current in avalanche and peak junction

temperature.

(IDM), the energy rating is specified at rated continuous cur-

rent (ID), in accordance with industry custom. The energy rat-

ing must be derated for temperature as shown in the

accompanying graph (Figure 12). Maximum energy at cur-

rents below rated continuous ID can safely be assumed to

equal the values indicated.