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Datasheet: DAC8552 (Maxim Integrated Products)

The DAC8552 isA 16-bit, dual channel, voltage output digital-to-analog converter (DAC) offering low power operation andA flexible serial host interface. Each on-chip precision output amplifier allows rail-to-rail output swing to be achieved over the supply range of 2.7V to 5.5V. The device supportsA standard 3-wire serial interface capable of operating with input data clock frequencies up to 30MHz for VDD = 5V.The DAC8552 requires an external reference voltage to set the output range of each DAC channel.

 

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Maxim Integrated Products

Document Outline

Burr Brown Products
from Texas Instruments
DAC8552
FEATURES
DESCRIPTION
APPLICATIONS
DAC A
DAC B
V
REF
V
DD
V
A
OUT
V
B
OUT
Power-Down
Control Logic
Resistor
Network
2
Channel
Select
Load
Control
8
Control Logic
GND
SYNC
SCLK
D
IN
16
24-Bit,
Serial-to-
Parallel
Shift
Register
Data
Buffer A
Data
Buffer B
DAC
A
Register
DAC
Register B
DAC8552
SLAS430 JULY 2006
16-BIT, DUAL CHANNEL, ULTRA-LOW GLITCH VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
Relative Accuracy: 4LSB
The DAC8552 is a 16-bit, dual channel, voltage
output digital-to-analog converter (DAC) offering low
Glitch Energy: 0.15nV-s
power operation and a flexible serial host interface.
MicroPower Operation:
Each
on-chip
precision
output
amplifier
allows
155
A per Channel at 2.7V
rail-to-rail output swing to be achieved over the
Power-On Reset to Zero-Scale
supply range of 2.7V to 5.5V. The device supports a
standard 3-wire serial interface capable of operating
Power Supply: 2.7V to 5.5V
with input data clock frequencies up to 30MHz for
16-Bit Monotonic Over Temperature
V
DD
= 5V.
Settling Time: 10
s to
0.003% FSR
The DAC8552 requires an external reference voltage
Ultra-Low AC Crosstalk: 100dB Typ
to set the output range of each DAC channel. Also
Low-Power Serial Interface With
incorporated into the device is a power-on reset
Schmitt-Triggered Inputs
circuit which ensures that the DAC outputs power up
at zero-scale and remain there until a valid write
On-Chip Output Buffer Amplifier With
takes place. The DAC8552 provides a flexible
Rail-to-Rail Operation
power-down
feature,
accessed
over
the
serial
Double-Buffered Input Architecture
interface, that reduces the current consumption of
Simultaneous or Sequential Output Update
the device to 700nA at 5V.
and Powerdown
The low-power consumption of this device in normal
Available in a Tiny MSOP-8 Package
operation
makes
it
ideally
suited
for
portable
battery-operated equipment and other low-power
applications. The power consumption is 0.5mW per
channel at 2.7V, reducing to 1
W in power-down
Portable Instrumentation
mode.
Closed-Loop Servo Control
The DAC8552 is available in a MSOP-8 package
Process Control
with a specified operating temperature range of
Data Acquisition Systems
40
C to +105
C.
Programmable Attenuation
PC Peripherals
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSP are trademarks of Motorola.
Microwire is a trademark of National Semiconductor.
PRODUCTION DATA information is current as of publication date.
Copyright 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
DAC8552
SLAS430 JULY 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGING/ORDERING INFORMATION
(1)
MAXIMUM
MAXIMUM
RELATIVE
DIFFERENTIAL
SPECIFICATION
TRANSPORT
ACCURACY
NONLINEARITY
PACKAGE
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
MEDIA,
PRODUCT
(LSB)
(LSB)
LEAD
DESIGNATOR
RANGE
MARKING
NUMBER
QUANTITY
DAC8552IDGKT
Tape and Reel, 250
DAC8552
12
1
MSOP-8
DGK
40
C to +105
C
D82
DAC8552IDGKR
Tape and Reel, 2500
(1)
For the most current package and ordering information, see the Package Option Addendum at the of this document, or see the TI
website at
www.ti.com
.
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
V
DD
to GND
0.3V to 6V
Digital input voltage to GND
0.3V to V
DD
+ 0.3V
V
OUTA
or V
OUTB
to GND
0.3V to V
DD
+ 0.3V
Operating temperature range
40
C to +105
C
Storage temperature range
65
C to +150
C
Junction temperature (T
J
max)
+150
C
Power dissipation
(T
J
max T
A
)/
JA
JA
thermal impedance
206
C/W
JC
thermal impedance
44
C/W
(1)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
V
DD
= 2.7V to 5.5V, all specifications 40
C to +105
C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE
(1)
Resolution
16
Bits
Relative accuracy
Measured by line passing through codes 513
4
12
LSB
and 64741
Differential nonlinearity
16-bit monotonic
0.35
1
LSB
Zero code error
Measured by line passing through codes 485
2.5
12
mV
and 64741
Zero code error drift
5
V/
C
Full-scale error
Measured by line passing through codes 485
0.1
0.5
% of FSR
and 64741
Gain error
Measured by line passing through codes 485
0.08
0.2
% of FSR
and 64741
Gain temperature coefficient
1
ppm of FSR/
C
PSRR
Output unloaded
0.75
mV/V
OUTPUT CHARACTERISTICS
(2)
Output voltage range
0
V
REF
V
(1)
Linearity calculated using a reduced code range of 513 to 64741. Output unloaded.
(2)
Specified by design and characterization, not production tested.
2
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DAC8552
SLAS430 JULY 2006
ELECTRICAL CHARACTERISTICS (continued)
V
DD
= 2.7V to 5.5V, all specifications 40
C to +105
C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
To
0.003% FSR 0200
H
to FD00
H
, R
L
= 2k
;
8
10
0pF < C
L
< 200pF
Output voltage settling time
s
R
L
= 2k
; C
L
= 500pF
12
Slew rate
1.8
V/
s
R
L
=
470
Capacitive load stability
pF
R
L
= 2k
1000
Code change glitch impulse
1LSB change around major carry
0.15
nV-s
Digital feedthrough
50k
series resistance on digital lines
0.15
nV-s
Full-scale swing on adjacent channel.
DC crosstalk
0.25
LSB
V
DD
= 5V, V
REF
= 4.096V
AC crosstalk
1kHz Sine wave
100
dB
DC output impedance
At mid-point input
1
V
DD
= 5V
50
Short circuit current
mA
V
DD
= 3V
20
Coming out of power-down mode V
DD
= 5V
2.5
s
Power-up time
Coming out of power-down mode V
DD
= 3V
5
s
AC PERFORMANCE
SNR
95
BW = 20kHz, V
DD
= 5V, f
OUT
= 1kHz,
THD
-85
1st 19 harmonics removed for SNR
dB
SFDR
87
calculation
SINAD
84
REFERENCE INPUT
V
REF
= V
DD
= 5.5V
90
120
Reference current
A
V
REF
= V
DD
= 3.6V
60
100
Reference input range
0
V
DD
V
Reference input impedance
62
k
LOGIC INPUTS
(3)
Input current
1
A
V
DD
= 5V
0.8
V
IN
L, Input LOW voltage
V
V
DD
= 3V
0.6
V
DD
= 5V
2.4
V
IN
H, Input HIGH voltage
V
V
DD
= 3V
2.1
Pin capacitance
3
pF
POWER REQUIREMENTS
V
DD
2.7
5.5
V
Input Code = 32768, no load, does not
I
DD
(normal mode)
include reference current
V
DD
= 3.6V to 5.5V
340
500
V
IH
= V
DD
and V
IL
= GND
A
V
DD
= 2.7V to 3.6V
310
480
I
DD
(all power-down modes)
V
DD
= 3.6V to 5.5V
0.7
2
V
IH
= V
DD
and V
IL
= GND
A
V
DD
= 2.7V to 3.6V
0.4
2
POWER EFFICIENCY
I
OUT
/I
DD
I
LOAD
= 2mA, V
DD
= 5V
89%
TEMPERATURE RANGE
Specified performance
40
+105
C
(3)
Specified by design and characterization, not production tested.
3
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PIN CONFIGURATION
V
DD
V
REF
V
OUT
B
V
OUT
A
GND
D
IN
SCLK
SYNC
1
2
3
4
8
7
6
5
DAC8552
DAC8552
SLAS430 JULY 2006
DGK PACKAGE
MSOP-8
(Top View)
PIN DESCRIPTIONS
PIN
NAME
FUNCTION
1
V
DD
Power supply input, 2.7V to 5.5V
2
V
REF
Reference voltage input
3
V
OUT
B
Analog output voltage from DAC B
4
V
OUT
A
Analog output voltage from DAC A
Level triggered SYNC input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes
LOW, it enables the input shift register and data is transferred on the falling edges of SCLK. The action specified by the
5
SYNC
8-bit control byte and 16-bit data word is executed following the 24th falling SCLK clock edge (unless SYNC is taken
HIGH before this edge in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by
the DAC8552). Schmitt-Trigger logic input.
6
SCLK
Serial Clock Input. Data can be transferred at rates up to 30MHz at 5V. Schmitt-Trigger logic input.
Serial Data Input. Data is clocked into the 24-bit input shift register on the falling edge of the serial clock input.
7
D
IN
Schmitt-Trigger logic input.
8
GND
Ground reference point for all circuitry on the part.
4
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SERIAL WRITE OPERATION
SCLK
1
24
SYNC
D
IN
DB23
DB0
DB23
t
8
t
6
t
3
t
2
t
1
t
7
t
9
t
5
t
4
TIMING CHARACTERISTICS
(1) (2)
DAC8552
SLAS430 JULY 2006
V
DD
= 2.7V to 5.5V, all specifications 40
C to +105
C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
DD
= 2.7V to 3.6V
50
t
1
(3)
SCLK cycle time
ns
V
DD
= 3.6V to 5.5V
33
V
DD
= 2.7V to 3.6V
13
t
2
SCLK HIGH time
ns
V
DD
= 3.6V to 5.5V
13
V
DD
= 2.7V to 3.6V
22.5
t
3
SCLK LOW time
ns
V
DD
= 3.6V to 5.5V
13
V
DD
= 2.7V to 3.6V
0
t
4
SYNC to SCLK rising edge setup time
ns
V
DD
= 3.6V to 5.5V
0
V
DD
= 2.7V to 3.6V
5
t
5
Data setup time
ns
V
DD
= 3.6V to 5.5V
5
V
DD
= 2.7V to 3.6V
4.5
t
6
Data hold time
ns
V
DD
= 3.6V to 5.5V
4.5
V
DD
= 2.7V to 3.6V
0
t
7
24th SCLK falling edge to SYNC rising edge
ns
V
DD
= 3.6V to 5.5V
0
V
DD
= 2.7V to 3.6V
50
t
8
Minimum SYNC HIGH time
ns
V
DD
= 3.6V to 5.5V
33
t
9
24th SCLK falling edge to SYNC falling edge
V
DD
= 2.7V to 5.5V
100
ns
(1)
All input signals are specified with t
R
= t
F
= 5ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2)
See Serial Write Operation timing diagram.
(3)
Maximum SCLK frequency is 30MHz at V
DD
= 3.6V to 5.5V and 20MHz at V
DD
= 2.7V to 3.6V.
5
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TYPICAL CHARACTERISTICS
8
6
4
2
0
-2
-4
-6
-8
LE(LSB)
0
8192
16384 24576 32768
Digital Input Code
40960 49152
57344 65536
1.0
0.5
0
-0.5
-1.0
DLE(LSB)
V
= 5V, V
= 4.9V, T = +25C
DD
REF
A
Channel A Output
8
6
4
2
0
-2
-4
-6
-8
LE(LSB)
0
8192
16384 24576 32768
Digital Input Code
40960 49152
57344 65536
1.0
0.5
0
-0.5
-1.0
DLE(LSB)
V
= 5V, V
= 4.9V, T = +25C
DD
REF
A
Channel B Output
8
6
4
2
0
-2
-4
-6
-8
LE(LSB)
0
8192
16384 24576 32768
Digital Input Code
40960 49152
57344 65536
1.0
0.5
0
-0.5
-1.0
DLE(LSB)
V
= 2.7V, V
= 2.5V, T = +25C
DD
REF
A
Channel A Output
8
6
4
2
0
-2
-4
-6
-8
LE(LSB)
0
8192
16384 24576 32768
Digital Input Code
40960 49152
57344 65536
1.0
0.5
0
-0.5
-1.0
DLE(LSB)
V
= 2.7V, V
= 2.5V, T = +25 C
DD
REF
A
Channel B Output
T
A
- Free-Air Temperature -
C
-7.5
-5.0
-2.5
0.0
2.5
5.0
7.5
-40
0
40
80
120
V
DD
= 5V
V
REF
= 4.99V
Zero-Scale Error - mV
CH B
CH A
T
A
- Free-Air Temperature -
C
-7.5
-5.0
-2.5
0.0
2.5
5.0
7.5
-40
0
40
80
120
V
DD
= 2.7V
V
REF
= 2.69V
Zero-Scale Error - mV
CH B
CH A
DAC8552
SLAS430 JULY 2006
At T
A
= +25
C, unless otherwise noted.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
Figure 1.
Figure 2.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
Figure 3.
Figure 4.
ZERO-SCALE ERROR vs TEMPERATURE
ZERO-SCALE ERROR vs TEMPERATURE
Figure 5.
Figure 6.
6
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T
A
- Free-Air Temperature -
C
-10
-5
0
5
-40
0
40
80
120
V
DD
= 5V
V
REF
= 4.99V
Full-Scale Error - mV
CH B
CH A
T
A
- Free-Air Temperature -
C
-10
-5
0
5
-40
0
40
80
120
V
DD
= 2.7V
V
REF
= 2.69V
Full-Scale Error - mV
CH B
CH A
I
SINK
- Sink Current - mA
0.000
0.025
0.050
0.075
0.100
0.125
0.150
0
2
4
6
8
10
V
REF
= V
DD
- 10mV
DAC loaded with 0000
H
V
O
- Output V
oltage - V
V
DD
= 2.7V
V
DD
= 5.5V
I
SOURCE
- Source Current - mA
4.0
4.4
4.8
5.2
5.6
6.0
0
2
4
6
8
10
V
REF
= V
DD
- 10mV
DAC loaded with FFFF
H
V
DD
= 5.5V
V
O
- Output V
oltage - V
I
Source Current
mA
SOURCE
-
-
1.5
1.8
2.1
2.4
2.7
3.0
0
2
4
6
8
10
V
OutputV
oltage
V
O
-
-
V
= 2.7 V
V
= V
10mV
DAC loaded with FFFF
DD
REF
DD
H
-
Digital Input Code
0
100
200
300
400
500
600
0
8192 16384 24576 32768 40960 49152 57344 65536
Reference Current Included
I
D
D
- Supply Current -
A
V
DD
= V
REF
= 3.6V
V
DD
= V
REF
= 5.5V
DAC8552
SLAS430 JULY 2006
TYPICAL CHARACTERISTICS (continued)
At T
A
= +25
C, unless otherwise noted.
FULL-SCALE ERROR vs TEMPERATURE
FULL-SCALE ERROR vs TEMPERATURE
Figure 7.
Figure 8.
SINK CURRENT CAPABILTY AT NEGATIVE RAIL
SOURCE CURRENT CAPABILITY AT POSITIVE RAIL
Figure 9.
Figure 10.
SOURCE CURRENT CAPABILITY AT POSITIVE RAIL
SUPPLY CURRENT vs DIGITAL INPUT CODE
Figure 11.
Figure 12.
7
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V
DD
- Supply Voltage - V
200
250
300
350
400
450
500
550
600
2.70
3.05
3.40
3.75
4.10
4.45
4.80
5.15
5.50
I
D
D
- Supply Current -
A
V
REF
= V
DD
, All DAC's Powered,
Reference Current Included, No Load
T
A
- Free-Air Temperature -
C
0
100
200
300
400
500
600
-40
0
40
80
120
I
D
D
- Supply Current -
A
Reference Current Included
V
DD
= V
REF
= 3.6V
V
DD
= V
REF
= 5.5V
V
LOGIC
- Logic Input Voltage - V
0
100
200
300
400
500
600
700
800
0.0
0.5
1.0
1.5
2.0
2.5
I
D
D
- Supply Current -
A
T
A
= 25
C, SYNC Input (All other inputs = GND)
CH A powered up; All other channels in powerdown
V
DD
= V
REF
= 2.7V
V
LOGIC
- Logic Input Voltage - V
0
400
800
1200
1600
2000
2400
0.0
1.0
2.0
3.0
4.0
5.0
I
D
D
- Supply Current -
A
T
A
= 25
C, SYNC Input (All other inputs = GND)
CH A powered up; All other channels in powerdown
V
DD
= V
REF
= 5.5V
-100
-90
-80
-70
-60
-50
-40
0
1
2
3
4
5
THD - T
otal Harmonic Distortion - dB
Output Tone - kHz
THD
2nd Harmonic
3rd Harmonic
-1dB FSR Digital Input, f
S
= 1MSPS
Measurement Bandwidth = 20kHz
V
DD
= 5V, V
REF
= 4.9V
-130
-110
-90
-70
-50
-30
-10
0
5000
10000
15000
20000
V
DD
= 5V, V
REF
= 4.096V
f
OUT
= 1kHz
f
CLK
= 1MSPS
f - Frequency - Hz
Gain - dB
DAC8552
SLAS430 JULY 2006
TYPICAL CHARACTERISTICS (continued)
At T
A
= +25
C, unless otherwise noted.
SUPPLY CURRENT vs SUPPLY VOLTAGE
SUPPLY CURRENT vs TEMPERATURE
Figure 13.
Figure 14.
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
Figure 15.
Figure 16.
TOTAL HARMONIC DISTORTION
vs
POWER SPECTRAL DENSITY
OUTPUT FREQUENCY
Figure 17.
Figure 18.
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84
86
88
90
92
94
96
98
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
SNR - Signal-to-Noise Ratio - dB
f - Output Frequency - kHz
V
DD
= V
REF
= 5V
-1dB FSR Digital Input, f
S
= 1MSPS
Measurement Bandwidth = 20kHz
100
150
200
250
300
350
100
1000
10000
100000
V
DD
= 5 V
V
REF
= 4.096
Code = 7FFF
No Load
nV/
Hz
- V
oltage Noise -
V
n
f - Frequency - Hz
Time (2 s/div)
m
V
= 5V
V
= 4.096V
From Code: D000
To Code: FFFF
DD
REF
Trigger Pulse 5V/div
Zoomed Rising Edge
1mV/div
Rising Edge
1V/div
Time (2 s/div)
m
V
= 5V
V
= 4.096V
From Code: FFFF
To Code: 0000
DD
REF
Trigger Pulse 5V/div
Zoomed Falling Edge
1mV/div
Falling
Edge
1V/div
Time (2 s/div)
m
V
= 5V
V
= 4.096V
From Code: 4000
To Code: CFFF
DD
REF
Trigger Pulse 5V/div
Zoomed Rising Edge
1mV/div
Rising
Edge
1V/div
Time (2 s/div)
m
V
= 5V
V
= 4.096V
From Code: CFFF
To Code: 4000
DD
REF
Trigger Pulse 5V/div
Zoomed Falling Edge
1mV/div
Falling
Edge
1V/div
DAC8552
SLAS430 JULY 2006
TYPICAL CHARACTERISTICS (continued)
At T
A
= +25
C, unless otherwise noted.
SIGNAL-TO-NOISE RATIO
vs
OUTPUT FREQUENCY
OUTPUT NOISE DENSITY
Figure 19.
Figure 20.
FULL-SCALE SETTLING TIME: 5V RISING EDGE
FULL-SCALE SETTLING TIME: 5V FALLING EDGE
Figure 21.
Figure 22.
HALF-SCALE SETTLING TIME: 5V RISING EDGE
HALF-SCALE SETTLING TIME: 5V FALLING EDGE
Figure 23.
Figure 24.
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Time (2 s/div)
m
V
= 2.7V
V
= 2.5V
From Code: 0000
To Code: FFFF
DD
REF
Trigger Pulse 2.7V/div
Zoomed Rising Edge
1mV/div
Rising
Edge
0.5V/div
Time (2 s/div)
m
V
= 2.7V
V
= 2.5V
From Code: FFFF
To Code: 0000
DD
REF
Trigger Pulse 2.7V/div
Zoomed Falling Edge
1mV/div
Falling
Edge
0.5V/div
Time (2 s/div)
m
V
= 2.7V
V
= 2.5V
From Code: 4000
To Code: CFFF
DD
REF
Trigger Pulse 2.7V/div
Zoomed Rising Edge
1mV/div
Rising
Edge
0.5V/div
Time (2 s/div)
m
V
= 2.7V
V
= 2.5V
From Code: CFFF
To Code: 4000
DD
REF
Trigger Pulse 2.7V/div
Zoomed Falling Edge
1mV/div
Falling
Edge
0.5V/div
Time (400ns/div)
V
= 5V
V
= 4.096V
From Code: 7FFF
To Code: 8000
Glitch: 0.08nV-s
DD
REF
V
(500
V/div)
m
O
U
T
Time (400ns/div)
V
= 5V
V
= 4.096V
From Code: 8000
To Code: 7FFF
Glitch: 0.16nV-s
Measured Worst Case
DD
REF
V
(500
V/div)
m
O
U
T
DAC8552
SLAS430 JULY 2006
TYPICAL CHARACTERISTICS (continued)
At T
A
= +25
C, unless otherwise noted.
FULL-SCALE SETTLING TIME: 2.7V RISING EDGE
FULL-SCALE SETTLING TIME: 2.7V FALLING EDGE
Figure 25.
Figure 26.
HALF-SCALE SETTLING TIME: 2.7V RISING EDGE
HALF-SCALE SETTLING TIME: 2.7V FALLING EDGE
Figure 27.
Figure 28.
GLITCH ENERGY: 5V, 1LSB STEP, RISING EDGE
GLITCH ENERGY: 5V, 1LSB STEP, FALLING EDGE
Figure 29.
Figure 30.
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Time (400ns/div)
V
= 5V
V
= 4.096V
From Code: 8000
To Code: 8010
Glitch: 0.04nV-s
DD
REF
V
(500
V/div)
m
O
U
T
Time (400ns/div)
V
= 5V
V
= 4.096V
From Code: 8010
To Code: 8000
Glitch: 0.08nV-s
DD
REF
V
(500
V/div)
m
O
U
T
Time (400ns/div)
V
= 5V
V
= 4.096V
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
DD
REF
V
(5mV/div)
O
U
T
Time (400ns/div)
V
= 5V
V
= 4.096V
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
DD
REF
V
(5mV/div)
O
U
T
Time (400ns/div)
V
= 2.7V
V
= 2.5V
From Code: 7FFF
To Code: 8000
Glitch: 0.08nV-s
DD
REF
V
(200
V/div)
m
O
U
T
Time (400ns/div)
V
= 2.7V
V
= 2.5V
From Code: 8000
To Code: 7FFF
Glitch: 0.16nV-s
Measured Worst Case
DD
REF
V
(200
V/div)
m
O
U
T
DAC8552
SLAS430 JULY 2006
TYPICAL CHARACTERISTICS (continued)
At T
A
= +25
C, unless otherwise noted.
GLITCH ENERGY: 5V, 16LSB STEP, RISING EDGE
GLITCH ENERGY: 5V, 16LSB STEP, FALLING EDGE
Figure 31.
Figure 32.
GLITCH ENERGY: 5V, 256LSB STEP, RISING EDGE
GLITCH ENERGY: 5V, 256LSB STEP, FALLING EDGE
Figure 33.
Figure 34.
GLITCH ENERGY: 2.7V, 1LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7V, 1LSB STEP, FALLING EDGE
Figure 35.
Figure 36.
11
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Time (400ns/div)
V
= 2.7V
V
= 2.5V
From Code: 8000
To Code: 8010
Glitch: 0.04nV-s
DD
REF
V
(200
V/div)
m
O
U
T
Time (400ns/div)
V
= 2.7V
V
= 2.5V
From Code: 8010
To Code: 8000
Glitch: 0.12nV-s
DD
REF
V
(200
V/div)
m
O
U
T
Time (400ns/div)
V
= 2.7V
V
= 2.5V
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
DD
REF
V
(5mV/div)
O
U
T
Time (400ns/div)
V
= 2.7V
V
= 2.5V
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
DD
REF
V
(5mV/div)
O
U
T
DAC8552
SLAS430 JULY 2006
TYPICAL CHARACTERISTICS (continued)
At T
A
= +25
C, unless otherwise noted.
GLITCH ENERGY: 2.7V, 16LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7V, 16LSB STEP, FALLING EDGE
Figure 37.
Figure 38.
GLITCH ENERGY: 2.7V, 256LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7V, 256LSB STEP, FALLING EDGE
Figure 39.
Figure 40.
12
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THEORY OF OPERATION
DAC SECTION
62k
GND
DAC Register
REF (+)
Register String
REF (-)
V
OUT
REF
V
50k
50k
V
OUT
A, B
+
V
REF
D
65536
(1)
RESISTOR STRING
To Output
Amplifier
(2x Gain)
R
DIVIDER
R
R
R
R
V
REF
V
REF
2
OUTPUT AMPLIFIER
SERIAL INTERFACE
DAC8552
SLAS430 JULY 2006
The architecture of each channel of the DAC8552
consists of a resistor-string DAC followed by an
output buffer amplifier.
Figure 41
shows a simplified
block diagram of the DAC architecture.
Figure 41. DAC8552 Architecture
The input coding for each device is unipolar straight
binary, so the ideal output voltage is given by:
where D = decimal equivalent of the binary code that
is loaded to the DAC register; it can range from 0 to
65535. V
OUT
A,B refers to channel A or B.
The resistor string section is shown in
Figure 42
. It is
simply a divide-by-2 resistor followed by a string of
resistors, each of value R. The code loaded into the
Figure 42. Resistor String
DAC register determines at which node on the string
the voltage is tapped off. This voltage is then applied
The write sequence begins by bringing the SYNC
to the output amplifier by closing one of the switches
line LOW. Data from the D
IN
line is clocked into the
connecting the string to the amplifier.
24-bit shift register on each falling edge of SCLK.
The serial clock frequency can be as high as 30MHz,
making the DAC8552 compatible with high speed
DSPs. On the 24th falling edge of the serial clock,
Each output buffer amplifier is capable of generating
the last data bit is clocked into the shift register and
rail-to-rail voltages on its output which approaches
the shift register is locked. Further clocking does not
an output range of 0V to V
DD
(gain and offset errors
change the shift register data. Once 24 bits are
must be taken into account). Each buffer is capable
locked into the shift register, the 8 MSBs are used as
of driving a load of 2k
in parallel with 1000pF to
control bits and the 16 LSBs are used as data. After
GND. The source and sink capabilities of the output
receiving the 24th falling clock edge, the DAC8552
amplifier can be seen in the typical characteristics.
decodes the 8 control bits and 16 data bits to
perform the required function, without waiting for a
SYNC rising edge. A new SPI sequence starts at the
The DAC8552 uses a 3-wire serial interface (SYNC,
next falling edge of SYNC. A rising edge of SYNC
SCLK, and D
IN
), which is compatible with SPITM and
before the 24-bit sequence is complete resets the
QSPTM, and MicrowireTM interface standards, as well
SPI interface; no data transfer occurs.
as most DSPs. See the Serial Write Operation timing
After the 24th falling edge of SCLK is received, the
diagram for an example of a typical write sequence.
SYNC line may be kept LOW or brought HIGH. In
either case, the minimum delay time from the 24th
falling SCLK edge to the next falling SYNC edge
must be met in order to properly begin the next
13
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POWER-ON RESET
INPUT SHIFT REGISTER
POWER-DOWN MODES
V
A,B
OUT
Amplifier
Resistor
String
DAC
Power-Down
Circuitry
Resistor
Network
SYNC INTERRUPT
DAC8552
SLAS430 JULY 2006
cycle. To assure the lowest power consumption of
the device, care should be taken that the levels are
The DAC8552 contains a power-on reset circuit that
as close to each rail as possible. (See the Typical
controls the output voltage during power-up. On
Characteristics section for the Supply Current vs
power-up, the DAC registers are filled with zeros and
Logic Input Voltage transfer characteristic curve).
the output voltages are set to zero-scale; they
remain there until a valid write sequence and load
command is made to the respective DAC channel.
This is useful in applications where it is important to
The input shift register of the DAC8552 is 24 bits
know the state of the output of each DAC output
wide (see
Figure 45
) and is made up of 8 control bits
while the device is in the process of powering up.
(DB16DB23) and 16 data bits (DB0DB15). The
first two control bits (DB22 and DB23) are reserved
No device pin should be brought high before power
and must be '0' for proper operation. LDA (DB20)
is applied to the device.
and LD B (DB21) control the updating of each analog
output with the specified 16-bit data value or power-
down command. Bit DB19 is a Don't Care bit, which
does not affect the operation of the DAC8552 and
The DAC8552 utilizes four modes of operation.
can be '1' or '0'. The following control bit, Buffer
These modes are accessed by setting two bits (PD1
Select (DB18), controls the destination of the data
and PD0) in the control Load action to one or both
(or power-down command) between DAC A and
DACs.
Table 1
shows how the state of the bits
DAC B. The final two control bits, PD0 (DB16) and
correspond to the register and performing a mode of
PD1 (DB17), select the power-down mode of one or
operation of each channel of the device. (Each DAC
both of the DAC channels. The four modes are
channel can be powered down simultaneously or
normal mode or any one of three power-down
independently of each other. Power-down occurs
modes.
A
more
complete
description
of
the
after proper data is written into PD0 and PD1 and a
operational modes of the DAC8552 can be found in
Load
command
occurs.)
See
the
Operation
the Power-Down Modes section. The remaining
Examples section for additional information.
sixteen bits of the 24-bit input word make up the data
bits. These are transferred to the specified Data
Table 1. Modes of Operation for the DAC8552
Buffer or DAC Register, depending on the command
PD1 (DB17)
PD0 (DB16)
OPERATING MODE
issued by the control byte, on the 24th falling edge of
0
0
Normal Operation
SCLK.
See
Table
2
and
Table
3
for
more
--
--
Power-down modes
information.
0
1
Output typically 1k
to GND
1
0
Output typically 100k
to GND
1
1
High impedance
When both bits are set to 0, the device works
normally with a typical power consumption of 450
A
at 5V. For the three power-down modes, however,
the supply current falls to 700nA at 5V (400nA at
3V). Not only does the supply current fall but the
output stage is also internally switched from the
output of the amplifier to a resistor network of known
values. This has the advantage that the output
Figure 43. Output Stage During Power-Down
impedance of the device is known while it is in
(High Impedance)
power-down mode. There are three different options
for power-down: The output is connected internally to
GND through a 1k
resistor, a 100k
resistor, or it is
left open-circuited (High-Impedance). The output
In a normal write sequence, the SYNC line is kept
stage is illustrated in
Figure 43
.
LOW for at least 24 falling edges of SCLK and the
addressed DAC register is updated on the 24th
All
analog
circuitry
is
shut
down
when
the
falling edge. However, if SYNC is brought HIGH
power-down mode is activated. Each DAC will exit
before the 24th falling edge, it acts as an interrupt to
power-down when PD0 and PD1 are set to 0, new
the write sequence; the shift register is reset and the
data is written to the Data Buffer, and the DAC
write sequence is discarded. Neither an update of
channel receives a Load command. The time to exit
the data buffer contents, DAC register contents or a
power-down is typically 2.5
s for V
DD
= 5V and 5
s
change
in
the
operating
mode
occurs
(see
for V
DD
= 3V (see the Typical Characteristics).
Figure 44
).
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SCLK
SYNC
D
IN
Invalid Write - Sync Interrupt:
SYNC HIGH before 24th Falling Edge
Valid Write - Buffer/DAC Update:
SYNC HIGH after 24th Falling Edge
DB23 DB22
DB0
DB23 DB22
DB1 DB0
24th
Falling
Edge
24th
Falling
Edge
1
2
1
2
DAC8552
SLAS430 JULY 2006
Figure 44. Interrupt and Valid SYNC Timing
DB23
DB12
0
0
LDB
LDA
X
Buffer Select
PD1
PD0
D15
D14
D13
D12
DB11
DB0
D11
D10
D9
D8
D7
D6
D5
D5
D3
D2
D1
D0
Figure 45. DAC8552 Data Input Register Format
Table 2. Control Matrix
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13D0
Don't
Buffer
MSB-2...
Reserved
Reserved
Load B
Load A
PD1
PD0
MSB
MSB-1
Care
Select
LSB
DESCRIPTION
0 = A,
(Always Write 0)
1 = B
0
0
0
0
X
#
0
0
Data
WR Buffer # w/Data
0
0
0
0
X
#
See
Table 3
X
WR Buffer # w/Power-down Command
0
0
0
1
X
#
0
0
Data
WR Buffer # w/Data and Load DAC A
0
0
0
1
X
0
See
Table 3
X
WR Buffer A w/Power-Down Command and LOAD DAC A
(DAC A Powered Down)
0
0
0
1
X
1
See
Table 3
X
WR Buffer B w/Power-Down Command and LOAD DAC A
0
0
1
0
X
#
0
0
Data
WR Buffer # w/Data and Load DAC B
0
0
1
0
X
0
See
Table 3
X
WR Buffer A w/Power-Down Command and LOAD DAC B
0
0
1
0
X
1
See
Table 3
X
WR Buffer B w/Power-Down Command and LOAD DAC B
(DAC B Powered Down)
0
0
1
1
X
#
0
0
Data
WR Buffer # w/Data and Load DACs A and B
0
0
1
1
X
0
See
Table 3
X
WR Buffer A w/Power-Down Command and Load DACs A and
B (DAC A Powered Down)
0
0
1
1
X
1
See
Table 3
X
WR Buffer B w/Power-Down Command and Load DACs A and
B (DAC B Powered Down)
Table 3. Power-Down Commands
D17
D16
OUTPUT IMPEDANCE POWER DOWN COMMANDS
PD1
PD0
0
1
1k
1
0
100k
1
1
High Impedance
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OPERATION EXAMPLES
DAC8552
SLAS430 JULY 2006
Example 1: Write to Data Buffer A; Through Buffer B; Load DACA Through DACB Simultaneously
1st -- Write to DataBuffer A:
Reserved
Reserved
LDB
LDA
DC
Buffer Select
PD1
PD0
DB15
--
DB1
DB0
0
0
0
0
X
0
0
0
D15
--
D1
D0
2nd -- Write to Data Buffer B and Load DAC A and DAC B simultaneously:
Reserved
Reserved
LDB
LDA
DC
Buffer Select
PD1
PD0
DB15
--
DB1
DB0
0
0
1
1
X
1
0
0
D15
--
D1
D0
The DACA and DACB analog outputs simultaneously settle to the specified values upon completion of the 2nd
write sequence. (The Load command moves the digital data from the data buffer to the DAC register at which
time the conversion takes place and the analog output is updated. Completion occurs on the 24th falling SCLK
edge after SYNC LOW.)
Example 2: Load New Data to DACA and DACB Sequentially
1st -- Write to Data Buffer A and Load DAC A: DACA output settles to specified value upon completion:
Reserved
Reserved
LDB
LDA
DC
Buffer Select
PD1
PD0
DB15
--
DB1
DB0
0
0
0
1
X
0
0
0
D15
--
D1
D0
2nd -- Write to Data Buffer B and Load DAC B: DACB output settles to specified value upon completion:
Reserved
Reserved
LDB
LDA
DC
Buffer Select
PD1
PD0
DB15
--
DB1
DB0
0
0
1
0
X
1
0
0
D15
--
D1
D0
After completion of the 1st write cycle, the DACA analog output settles to the voltage specified; upon completion
of write cycle 2, the DACB analog output settles.
Example 3: Power-Down DACA to 1k
and Power-Down DACB to 100k
Simultaneously
1st -- Write power-down command to Data Buffer A:
Reserved
Reserved
LDB
LDA
DC
Buffer Select
PD1
PD0
DB15
--
DB1
DB0
0
0
0
0
X
0
0
1
Don't Care
2nd -- Write power-down command to Data Buffer B and Load DACA and DACB simultaneously:
Reserved
Reserved
LDB
LDA
DC
Buffer Select
PD1
PD0
DB15
--
DB1
DB0
0
0
1
1
X
1
1
0
Don't Care
The DACA and DACB analog outputs simultaneously power-down to each respective specified mode upon
completion of the 2nd write sequence.
Example 4: Power-Down DACA and DACB to High-Impedance Sequentially:
1st -- Write power-down command to Data Buffer A and Load DAC A: DAC A output = Hi-Z:
Reserved
Reserved
LDB
LDA
DC
Buffer Select
PD1
PD0
DB15
--
DB1
DB0
0
0
0
1
X
0
1
1
Don't Care
2nd -- Write power-down command to Data Buffer B and Load DAC B: DAC B output = Hi-Z:
Reserved
Reserved
LDB
LDA
DC
Buffer Select
PD1
PD0
DB15
--
DB1
DB0
0
0
1
0
X
1
1
1
Don't Care
The DACA and DACB analog outputs sequentially power-down to high-impedance upon completion of the 1st
and 2nd write sequences, respectively.
16
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MICROPROCESSOR INTERFACING
DAC8552 to 8051 INTERFACE
DAC8552 to 68HC11 INTERFACE
68HC11
(1)
PC7
SCK
MOSI
SYNC
SCLK
D
IN
(1)
DAC8552
(1)Additional pins omitted for clarity.
80C51/80L51
(1)
P3.3
TXD
RXD
(1)
SYNC
SCLK
D
IN
(1)Additional pins omitted for clarity.
DAC8552
DAC8552 to TMS320 DSP INTERFACE
DAC8552 to Microwire INTERFACE
SYNC
SCLK
D
IN
Microwire
TM
CS
SK
SO
(1)
(1) Additional pins omitted for clarity.
Microwire is a registered trademark of National Semiconductor.
DAC8552
TMS320 DSP
SYNC
D
IN
SCLK
FSX
DX
CLKX
V
DD
V
OUT
A
V
OUT
B
Output A
Output B
Reference
Input
V
REF
GND
0.1
F
1
F to 10
F
Positive Supply
0.1
F
10
F
DAC8552
DAC8552
SLAS430 JULY 2006
Figure 46
shows a serial interface between the
Figure 48
shows a serial interface between the
DAC8552 and a typical 8051-type microcontroller.
DAC8552 and the 68HC11 microcontroller. SCK of
The setup for the interface is as follows: TXD of the
the 68HC11 drives the SCLK of the DAC8552, while
8051 drives SCLK of the DAC8552, while RXD
the MOSI output drives the serial data line of the
drives the serial data line of the device. The SYNC
DAC. The SYNC signal is derived from a port line
signal is derived from a bit-programmable pin on the
(PC7), similar to the 8051 diagram.
port of the 8051. In this case, port line P3.3 is used.
When data is to be transmitted to the DAC8552,
P3.3 is taken LOW. The 8051 transmits data in 8-bit
bytes; thus only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is left
LOW after the first eight bits are transmitted, then a
second and third write cycle is initiated to transmit
the remaining data. P3.3 is taken HIGH following the
completion of the third write cycle. The 8051 outputs
Figure 48. DAC8552 to 68HC11 Interface
the serial data in a format which presents the LSB
first, while the DAC8552 requires its data with the
MSB as the first bit received. The 8051 transmit
The 68HC11 should be configured so that its CPOL
routine must therefore take this into account, and
bit is 0 and its CPHA bit is 1. This configuration
mirror the data as needed
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data is being
transmitted to the DAC, the SYNC line is held LOW
(PC7). Serial data from the 68HC11 is transmitted in
8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. (Data is transmitted
MSB first.) In order to load data to the DAC8552,
PC7 is left LOW after the first eight bits are
transferred, then a second and third serial write
operation is performed to the DAC. PC7 is taken
Figure 46. DAC8552 to 80C51/80L51 Interface
HIGH at the end of this procedure.
Figure 49
shows the connections between the
Figure 47
shows an interface between the DAC8552
DAC8552 and a TMS320 digital signal processor. By
and any Microwire compatible device. Serial data is
decoding the FSX signal, multiple DAC8552s can be
shifted out on the falling edge of the serial clock and
connected to a single serial port of the DSP.
is clocked into the DAC8552 on the rising edge of
the SK signal.
Figure 47. DAC8552 to Microwire Interface
Figure 49. DAC8552 to TMS320 DSP
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APPLICATION INFORMATION
CURRENT CONSUMPTION
OUTPUT VOLTAGE STABILITY
DRIVING RESISTIVE AND CAPACITIVE
SETTLING TIME AND OUTPUT GLITCH
DIFFERENTIAL AND INTERGRAL
CROSSTALK AND AC PERFORMANCE
USING REF02 AS A POWER SUPPLY FOR
DAC8552
SLAS430 JULY 2006
The DAC8552 typically consumes 170
A at V
DD
=
The DAC8552 exhibits excellent temperature stability
5 V and 155
A at V
DD
= 2.7V for each active
of 5ppm/
C typical output voltage drift over the
channel, excluding reference current consumption.
specified temperature range of the device. This
Additional current consumption can occur at the
enables the output voltage of each channel to stay
digital inputs if V
IH
<< V
DD
. For most efficient power
within
a
25
V
window
for
a
1
C
ambient
operation, CMOS logic levels are recommended at
temperature change.
the digital input to the DAC.
Good
power-supply
rejection
ratio
(PSRR)
In power-down mode, typical current consumption is
performance reduces supply noise present on V
DD
700nA. A delay time of 10ms to 20ms after a
from appearing at the outputs. Combined with good
power-down command is issued to the DAC is
DC noise performance and true 16-bit differential
typically sufficient for the power-down current to drop
linearity, the DAC8552 becomes an ideal choice for
below 10
A.
closed-loop control applications.
LOADS
PERFORMANCE
The DAC8552 output stage is capable of driving
The DAC8552 settles to
0.003% of its full-scale
loads of up to 1000 pF while remaining stable. Within
range within 10
s, driving a 200pF, 2k
load. For
the offset and gain error margins, the DAC8552 can
good settling performance the outputs should not
operate rail-to-rail when driving a capacitive load.
approach the top and bottom rails. Small signal
Resistive loads of 2k
can be driven by the
settling time is under 1
s, enabling data update rates
DAC8552 while achieving good load regulation.
exceeding 1MSPS for small code changes.
When the outputs of the DAC are driven to the
Many
applications
are
sensitive
to
undesired
positive rail under resistive loading, the PMOS
transient signals such as glitch. The DAC8552 has a
transistor of each Class-AB output stage can enter
proprietary, ultra-low glitch architecture addressing
into the linear region. When this occurs, the added
such
applications.
Code-to-code
glitches
rarely
IR
voltage
drop
deteriorates
the
linearity
exceed 1mV and they last under 0.3
s. Typical glitch
performance of the DAC. This only occurs within
energy is an outstanding 0.15nV-s. Theoretical worst
approximately the top 100mV of the DACs output
cast glitch should occur during a 256LSB step, but it
voltage
characteristic.
Under
resistive
loading
is so low, it cannot be detected.
conditions, good linearity is preserved as long as the
output voltage is at least 100 mV below the VDD
voltage.
NONLINEARITY
The DAC8552 uses precision, thin-film resistors to
achieve monotonicity and good linearity. Typical
The DAC8552 architecture uses separate resistor
linearity error is
4LSBs;
0.3mV error for a 5V
strings for each DAC channel in order to achieve
range. Differential linearity is typically
0.35LSBs,
ultra-low crosstalk performance. DC crosstalk seen
27
V error for a consecutive code change.
at one channel during a full-scale change on the
neighboring channel is typically less than 0.5 LSBs.
The AC crosstalk measured (for a full-scale, 1kHz
DAC8552
sine wave output generated at one channel, and
measured at the remaining output channel) is
Due to the extremely low supply current required by
typically under 100dB.
the DAC8552, a possible configuration is to use a
REF02 +5V precision voltage reference to supply the
In addition, the DAC8552 can achieve typical AC
required voltage to the DAC8552s supply input as
performance of 96dB signal-to-noise ratio (SNR) and
well as the reference input, as shown in
Figure 50
.
-85dB total harmonic distortion (THD), making the
This is especially useful if the power supply is quite
DAC8552 a solid choice for applications requiring
noisy or if the system supply voltages are at some
high SNR at output frequencies at or below 10kHz.
value other than 5V. The REF02 will output a steady
supply voltage for the DAC8552. If the REF02 is
18
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V
OUT
A, B
+
V
REF
D
65536
R1
)
R2
R1
*
V
REF
R2
R1
V
OUT
A, B
+
10
D
65536
*
5 V
(3)
LAYOUT
REF02
3-Wire
Serial
Interface
+5V
1.34mA
V
DD
, V
REF
V
OUT
= 0V to 5V
SYNC
SCLK
D
IN
+15
DAC8552
BIPOLAR OPERATION USING THE DAC8552
V
DD
, V
REF
V
OUT
A,B
R
1
10k
R
2
10k
+5V
10
F
0.1
F
5V
OPA703
DAC8552
-
6V
+6V
NOTE: Other pins omitted for clarity.
DAC8552
SLAS430 JULY 2006
used, the current it needs to supply to the DAC8552
is 340
A typical and 500
A max for V
DD
= 5V. When
a DAC output is loaded, the REF02 also needs to
where D represents the input code in decimal
supply the current to the load. The typical current
(065535).
required (with a 5k
load on a given DAC output) is:
340
A + (5V/5k
) = 1.34mA
With V
REF
= 5 V, R1 R2 = 10k
.
This is an output voltage range of
5V with 0000
H
corresponding
to
a
5V
output
and
FFFF
H
corresponding to a 5V output. Similarly, using V
REF
=
2.5V, a
2.5V output voltage range can be achieved.
A precision analog component requires careful
layout,
adequate
bypassing,
and
clean,
well-regulated power supplies.
The DAC8552 offers single-supply operation, and it
will often be used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal
processors. The more digital logic present in the
design and the higher the switching speed, the more
Figure 50. REF02 as a Power Supply to the
difficult it will be to keep digital noise from appearing
DAC8552
at the output.
Due to the single ground pin of the DAC8552, all
return currents, including digital and analog return
currents for the DAC, must flow through a single
The DAC8552 has been designed for single-supply
point. Ideally, GND would be connected directly to an
operation but a bipolar output range is also possible
analog ground plane. This plane would be separate
using the circuit in
Figure 51
. The circuit shown will
from
the
ground
connection
for
the
digital
give an output voltage range of
V
REF
. Rail-to-rail
components until they were connected at the power
operation at the amplifier output is achievable using
entry point of the system.
an amplifier such as the OPA703, see
Figure 51
.
The power applied to V
DD
should be well regulated
and low noise. Switching power supplies and DC/DC
converters will often have high-frequency glitches or
spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes
as their internal logic switches states. This noise can
easily couple into the DAC output voltage through
various paths between the power connections and
analog output.
As with the GND connection, V
DD
should be
connected to a positive power-supply plane or trace
that is separate from the connection for digital logic
Figure 51. Bipolar Operation with the DAC8552
until they are connected at the power entry point. In
addition, a 1
F to 10
F capacitor in parallel with a
The output voltage for any input code can be
0.1
F bypass capacitor is strongly recommended. In
calculated as follows:
some
situations,
additional
bypassing
may
be
required, such as a 100
F electrolytic capacitor or
even
a
Pi
filter
made
up
of
inductors
and
capacitorsall designed to essentially low-pass filter
the supply, removing the high-frequency noise.
19
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
DAC8552IDGKR
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DAC8552IDGKRG4
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DAC8552IDGKT
ACTIVE
MSOP
DGK
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DAC8552IDGKTG4
ACTIVE
MSOP
DGK
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jul-2006
Addendum-Page 1
IMPORTANT NOTICE
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