2.3dB and an associated gain of 15dB was fabricated in a standard silicon bipolar transistor
array. It dissipates 5.2mW from a 3V supply including the bias circuitry. Input return loss and
isolation are -9dB and -20dB, respectively.
manufacturers are trying to replace as many discrete devices as possible with high-density ICs
to be competitive in size, weight, power dissipation, and price. In a number of recent papers
low power LNAs for S-band have been described [1,2,3]. These LNAs were fabricated using
some sophisticated GaAs full-custom processes. Since the high frequency performance of state-
of-the-art silicon bipolar processes are continuously improving lowcost semi-custom arrays
with a limited choice of components provide a reasonable solution for RF applications.
1.9GHz silicon LNA which draws a total current of 1.75mA including bias circuit.
eliminates the need for coupling capacitors. The current of the first stage is set by a resistive
parallel feedback (R3 and R4), which is connected to the external matching inductor (L1) such
that no noise degradation occurs. Thus, only a single supply voltage is required. This feedback
also improves both the bias and RF stability of the amplifier.
noise parameter data of the active device. Good agreement between simulated and measured
performance is found as shown in
Figure 2. Simulated vs. measured gain and input return loss
the noise figure from 700MHz up to 2GHz. The best 50W noise figure of 2.3dB is achieved
between 1.7 and 2.3 GHz. Note that the active device has a minimum noise figure of 1.5dB at
Figure 3. Measured gain and noise figure (VCC = 3V, ICC = 1.75mA (bold line:
average noise figure)
corresponding gain/DC-power figure of merit is 2.9dB/mW. Compared to other L-band LNAs,
this design shows low power consumption and a competitive noise figure as seen from
Figure 4. Gain to DC power ratio plotted versus noise figure for several state-of-the-art
L- and S-band LNAs
from 2.7 to 5V the noise figure remains between 2.2 and 2.5dB.
an output compression point of -9dBm. The third order intermodulation intercept point is
measured at -21dBm input power. This is adequate for DECT handheld terminal.
Figure 5. shows a photograph of the lower right part of the 1.9 x 1.8 mm
bonded to the printed input and output matching inductors.
Figure 6. Photograph of the Quickchip mounted on the test substrate. On the right are
the printed inductors for input and output matching.
figure of 2.3dB along with a 15dB gain. The power consumption is only 5.2mW resulting in a
high gain/DC-power figure of merit of 2.9dB/mW. The design was done on a transistor array
showing almost no performance degradation relative to full custom design.
for wireless communications", IEEE 1993 GaAs IC Symposium, pp. 49 - 51
 M. Nakatsugawa, Y. Yamaguchi, M. Muraguchi, "An L-band ultra low power consumption
monolithic low noise amplifier", IEEE 1993 GaAs IC Symposium, pp. 1745 - 1750