HIGH-SPEED SIGNAL PROCESSING
input bandwidth, the MAX104/6/8 family of data converters offers both sampling speed and signal
bandwidth for applications where these parameters are of the utmost importance. At their introduction in
1999, this family of high-speed analog-to-digital converters (ADCs) set a new standard for dynamic
performance requirements in high-frequency, wide-bandwidth applications. The following article outlines
the advantages of this family of ADCs and describes their impact and importance on digital
communications, DSOs and fast data acquisition systems.
standard for performance in high-frequency, high-bandwidth digital communications receivers, digital
oscilloscopes, and high-speed data-acquisition systems.
bandwidth track/hold (T/H) amplifier (Figure 1) with a high-speed quantizer that supports accurate
digitizing of wideband analog input signals from DC to 2.2GHz. It is based on Maxim's GST-2 Giga-Speed
silicon-bipolar process technology. This high-speed, self-aligned double-polysilicon process has been
developed for high-density, high-performance circuits. It employs many of the features, such as trench
isolation, that are incorporated in Maxim's lower performance GST-1 process.
with a high-speed quantizer.
integrated-circuit process (such as a transition frequency of 27GHz for NPN transistors, a three-metal
interconnect system, small geometry, and precision laser-trimmed nickel-chrome (NiCr) thin-film
limited to no more than their maximum sampling frequency to improve noise performance. One example is
the signal-to-noise ratio (SNR). This limited input bandwidth may rule out use in applications where
bandwidths of interest in the input spectrum are higher, and an undersampling approach is needed. Also, if
the input signal is changing rapidly during conversion, the effective number of bits (ENOB) and SNR will
be reduced. The MAX104's on-chip 2.2GHz full-power-bandwidth T/H amplifier (Figure 2) increases
dynamic performance significantly and supports more precise capture of fast analog data at extremely high
connecting the bandgap reference's output contact (REFOUT) to the in-phase input (REFIN) of the internal
reference amplifier. The negative input of this amplifier is internally tied to the reference ground (GNDR).
The REFOUT port can provide a current of up to 2.5mA for external devices. This is enough drive for two
MAX104s configured for interleaved operation (to achieve a sampling rate of 2 gigasamples per second, or
2Gsps). Since the bandgap reference source is internally compensated, external bypass components are not
needed with REFOUT connections.
REFOUT left floating. The external reference may then be used to adjust the full-scale range of the
scale signal input range of 500mV peak-to-peak. Obtaining a full-scale digital output with a differential
input requires 250mV applied between the positive (VIN+) and the negative input (VIN-) pins. Midscale
digital output codes occur at an input of 0V.
(VIN+). The high-performance differential T/H amplifier enables the MAX104 to be used in single-ended
input configurations without any degradation in dynamic performance. For a typical single-ended
configuration, the analog input signal is coupled to the T/H amplifier stage at the in-phase input pad
(VIN+), while the inverted phase input (VIN-) pad is referenced to ground. Single-ended operation
supports an input amplitude of 500mV peak-to-peak, centered at approximately 0V. For minimizing
250MHz, 500MHz (Figure 4), and 1GHz (Figure 5) with a sampling rate of 1Gsps for differential and
single-ended analog input operation, the MAX104 solves one of the most perplexing problems in high-
speed ADC applications-the need for costly, space-consuming, single-ended-to-differential signal-
conversion circuitry. Now, applications requiring single-ended signal sources can just feed this signal into
the VIN+ pin and terminate the VIN- pin through a 50
a sampling rate of 1Gsps and an analog input frequency of 125MHz.
a sampling rate of 1Gsps.
differential operation with very flexible input-drive requirements. Each clock input is terminated with an
on-chip, laser-trimmed, 50
(ECL) drive levels.
small-amplitude sine-wave sources. The MAX104 was designed for single-ended operation, maintaining
superior dynamic performance when using low-phase-noise sine-wave clock input signals with as little as
a single clock input. The MAX104 can accommodate clock amplitudes up to 1V (2V peak-to-peak) with
the clock-termination return connected to ground. The dynamic performance of the ADC is essentially
unaffected by clock signal amplitudes from 100mV to 1V.
termination voltage to -2V. To maintain the best performance, a very- high-speed differential ECL driver
should be used.
clock inputs are AC coupled. A single-ended ECL drive can also be used if the undriven clock input is
connected to the ECL VTT voltage (nominally -1.3V).
circuitry provides three different modes of operation. The demux operation is controlled by two transistor-
transistor-logic (TTL)/complementary-metal-oxide-semiconductor (CMOS)-compatible digital inputs:
DEMUXEN, which activates or deactivates the internal demux, and DIVSELECT, which selects one of
three demux modes (DIV1, DIV2, or DIV4).
outputs are presented in dual 8-bit format with two consecutive samples in the primary and auxiliary output
operation of the MAX104 at sampling speeds up to 500 megasamples per second (Msps). In this mode, the
internal demux is disabled and the sampled data are presented to the primary output port only. To consume
less power, the auxiliary port can be shut down by two separate inputs (AUXEN1 and AUXEN2). To save
additional power, the external 50
outputs data at one quarter of the input sampling rate. This mode is particularly useful for system
debugging using the resulting slower output data rates. With an input clock of 1GHz, the effective output
data rate will be reduced to 250MHz in this mode.
ADCs to be synchronized for proper interleaving operation. In addition, the reset signal appears as an
external demux reset output for synchronizing external demuxes.
driving controlled low-impedance lines. The PECL outputs can be powered from +3V to +5.25V DC
supply voltages. PECL outputs on the MAX104 are typically terminated with a parallel 50
Outputs DREADY+ and DREADY- are data-ready true and complementary outputs, supplying the data
supplying a synchronous clock for downstream digital circuitry, such as demuxes or high-speed memory
devices. Data changes are triggered on the rising edge of the DREADY clock.
are the reset-out true and complementary outputs provided to reset downstream circuitry.
Amkor/Anam (Chandler, AZ) that measures 25mm x 25mm. The MAX104 provides an on-board 1:2
demux function, slowing data rates to 500Mbps supplied on two ports. The package features 50
operating frequencies. In addition, the package enables a large number of solder balls to be dedicated to
power supplies and ground. With a thickness of only 1.4mm, this 1.27mm pitch ESBGA package saves
circuit-board space while providing excellent thermal performance. In many applications, the MAX104 can
be used without a heat sink.
instantaneous value from a fast-moving signal, such as in a high-speed data acquisition (DAQ) application,
or to digitize a complex high-frequency, high-bandwidth signal. One example of this is in wideband digital
receivers for digital base stations. In this case, signal bandwidths that exceed 300MHz are allowed to pass
through the receiver intermediate-frequency (IF) stages to the demodulator. At this point, the information
bandwidth may be filtered and amplified before being presented to the ADC front end. This approach,
known as block or direct downconversion, requires that the input bandwidth of the ADC be sufficiently flat
to prevent distortions and nonlinearities in the resulting digital representation. The high-speed data stream
thus created is then presented to a digital demodulator which separates the individual channels and extracts
the modulated information.
frequencies below (e.g., at 125MHz and 250MHz) and well above the Nyquist frequency (e.g., operating at