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Datasheet: 5962-9067801MXC (Intersil Corporation)

High Performance Microprocessor with Memory Management and Protection

 

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Intersil Corporation
128
TM
80C286/883
High Performance Microprocessor with Memory
Management and Protection
Description
The Intersil 80C286/883 is a static CMOS version of the
NMOS 80286 microprocessor. The 80C286/883 is an
advanced, high-performance microprocessor with specially
optimized capabilities for multiple user and multi-tasking sys-
tems. The 80C286/883 has built-in memory protection that
supports operating system and task isolation as well as pro-
gram and data privacy within tasks. The 80C286/883
includes memory management capabilities that map 230
(one gigabyte) of virtual address space per task into 2
24
bytes (16 megabytes) of physical memory.
The 80C286/883 is upwardly compatible with 80C86 and
80C88 software (the 80C286/883 instruction set is a super-
set of the 80C86/80C88 instruction set). Using the 80C286/
883 real address mode, the 80C286/883 is object code com-
patible with existing 80C86 and 80C88 software. In pro-
tected virtual address mode, the 80C286/883 is source code
compatible with 80C86 and 80C88 software but may require
upgrading to use virtual address as supported by the
80C286/883's integrated memory management and protec-
tion mechanism. Both modes operate at full 80C286/883
performance and execute a superset of the 80C86 and
80C88 instructions.
The 80C286/883 provides special operations to support the
efficient implementation and execution of operating systems.
For example, one instruction can end execution of one task,
save its state, switch to a new task, load its state, and start
execution of the new task. The segment-not-present excep-
tion and restartable instructions.
Features
This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
Compatible with NMOS 80286/883
Static CMOS Design for Low Power Operation
- ICCSB = 5mA Maximum
- ICCOP = 185mA Maximum (80C286-10/883)
- ICCOP = 220mA Maximum (80C286-12/883)
Large Address Space
- 16 Megabytes Physical
- 1 Gigabyte Virtual per Task
Integrated Memory Management, Four-Level Memory
Protection and Support for Virtual Memory and
Operating Systems
Two 80C86 Upward Compatible Operating Modes
- 80C286/883 Real Address Mode
- Protected Virtual Address Mode
Compatible with 80287 Numeric Data Co-Processor
March 1997
Ordering Information
PACKAGE
TEMP. RANGE
10MHz
12.5MHz
16MHz
20MHz
25MHz
PKG. NO.
68 Pin PGA
0
o
C to +70
o
C
-
CG80C286-12
CG80C286-16
CG80C286-20
-
G68.B
-40
o
C to +85
o
C IG80C286-10
IG80C286-12
-
-
-
G68.B
-55
o
C to +125
o
C MG80C286-10/883 MG80C286-12/883
-
-
-
G68.B
5962-9067801MXC 5962-9067802MXC
-
-
-
G68.B
FN2948.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002. All Rights Reserved
129
80C286/883
Pinout
68 LEAD PGA, COMPONENT PAD VIEW
As viewed from underside of the component when mounted on the board.
P.C. BOARD VIEW
As viewed from the component side of the P.C. board.
68
66
64
62
60
58
56
54
52
53
51
55
57
59
61
63
65
67
2
1
3
5
7
9
10
4
6
8
12
11
13
14
16
15
17
19
18
21
20
22
24
26
28
30
32
34
23
25
27
29
31
33
36
35
37
38
40
39
41
42
44
43
45
46
48
47
49
50
E
RRO
R
D7
D6
D5
D4
D3
D2
D1
D0
NC
S1
P
E
ACK
A2
2
A2
1
A1
9
A1
7
A1
5
A1
2
D0
A1
CLK
RESET
A4
A6
A8
A10
A12
ERROR
NC
INTR
NMI
PEREQ
READY
HLDA
M/IO
NC
NC
BUSY
NC
NC
V
SS
V
CC
HOLD
COD/INTA
LOCK
D1
5
D1
4
D1
3
D1
2
D1
1
D1
0
D9
D8
V
SS
BHE
NC
S0
A2
3
V
SS
A2
0
A1
8
A1
6
A1
4
A0
A2
V
CC
A3
A5
A7
A9
A11
A13
PIN 1 INDICATOR
68
66
64
62
60
58
56
54
52
53
51
55
57
59
61
63
65
67
2
1
3
5
7
9
10
4
6
8
12
11
13
14
16
15
17
19
18
21
20
22
24
26
28
30
32
34
23
25
27
29
31
33
36
35
37
38
40
39
41
42
44
43
45
46
48
47
49
50
E
RRO
R
D7
D6
D5
D4
D3
D2
D1
D0
NC
S1
P
E
ACK
A2
2
A2
1
A1
9
A1
7
A1
5
A1
2
D0
A1
CLK
RESET
A4
A6
A8
A10
A12
ERROR
NC
INTR
NMI
PEREQ
READY
HLDA
M/IO
NC
NC
BUSY
NC
NC
V
SS
V
CC
HOLD
COD/INTA
LOCK
D1
5
D1
4
D1
3
D1
2
D1
1
D1
0
D9
D8
V
SS
BHE
NC
S0
A2
3
V
SS
A2
0
A1
8
A1
6
A1
4
A0
A2
V
CC
A3
A5
A7
A9
A11
A13
PIN 1 INDICATOR
130
80C286/883
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage Applied. . . . . . GND -1.0V to V
CC
+1.0V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65
o
C to +150
o
C
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300
o
C
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical)
JA
JC
PGA Package . . . . . . . . . . . . . . . . . . . . .
35
o
C/W
6
o
C/W
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22,500 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range. . . . . . . . . . . . . . . . -55
o
C to +125
o
C
System Clock (CLK) RISE Time (From 1.0V to 3.6V . . . . 8ns (Max)
System Clock (CLK) FALL Time (from 3.6V to 1.0V) . . . . 8ns (Max)
Input RISE and FALL Time (From 0.8V to 2.0V
80C286-10/883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
80C286-12/883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8ns (Max)
TABLE 1. 80C286/883 D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
CONDITIONS
GROUP A
SUB-
GROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Input LOW Voltage
V
IL
V
CC
= 4.5V
1, 2, 3
-55
o
C
T
A
+125
o
C
-0.5
0.8
V
Input HIGH Voltage
V
IH
V
CC
= 5.5V
1, 2, 3
-55
o
C
T
A
+125
o
C
2.0
V
CC
+0.5
V
CLK Input LOW Voltage
V
ILC
V
CC
= 4.5V
1, 2, 3
-55
o
C
T
A
+125
o
C
-0.5
1.0
V
CLK Input HIGH Voltage
V
IHC
V
CC
= 5.5V
1, 2, 3
-55
o
C
T
A
+125
o
C
3.6
V
CC
+0.5
V
Output LOW Voltage
V
OL
I
OL
= 2.0mA, V
CC
= 4.5V
1, 2, 3
-55
o
C
T
A
+125
o
C
-
0.4
V
Output HIGH Voltage
V
OH
I
OH
= -2.0mA, V
CC
= 4.5V
1, 2, 3
-55
o
C
T
A
+125
o
C
3.0
-
V
I
OH
= -100
A, V
CC
= 4.5V
V
CC
-0.4
-
V
Input Leakage Current
I
I
V
IN
= GND or V
CC
,
V
CC
= 5.5V,
Pins 29, 31, 57, 59, 61,
63-64
1, 2, 3
-55
o
C
T
A
+125
o
C
-10
10
A
Input Sustaining Current
LOW
I
BHL
V
CC
= 4.5V and 5.5V,
V
IN
= 1.0V, Note 1
1, 2, 3
-55
o
C
T
A
+125
o
C
38
200
A
Input Sustaining Current
HIGH
I
BHH
V
CC
= 4.5V and 5.5V,
V
IN
= 3.0V, Note 2
1, 2, 3
-55
o
C
T
A
+125
o
C
-50
-400
A
Input Sustaining Current
on BUSY and ERROR
Pins
I
SH
V
CC
= 4.5V and 5.5V
V
IN
= GND, Note 5
1, 2, 3
-55
o
C
T
A
+125
o
C
-30
-500
A
Output Leakage Current
I
O
V
O
= GND or V
CC
V
CC
= 5.5V,
Pins 1, 7-8, 10-28, 32-34
1, 2, 3
-55
o
C
T
A
+125
o
C
-10
10
A
Active Power Supply
Current
I
CCOP
80C286-10/883, Note 4
1, 2, 3
-55
o
C
T
A
+125
o
C
-
185
mA
80C286-12/883, Note 4
-
220
mA
Standby Power
Supply Current
I
CCSB
V
CC
= 5.5V, Note 3
1, 2, 3
-55
o
C
T
A
+125
o
C
-
5
mA
NOTES:
2. I
BHL
should be measured after lowering V
IN
to GND and then raising to 1.0V on the following pins: 36-51, 66, 67.
3. I
BHH
should be measured after raising V
IN
to V
CC
and then lowering to 3.0V on the following pins: 4-6, 36-51, 66-68.
4. I
CCSB
should be tested with the clock stopped in phase two of the processor clock cycle. V
IN
= V
CC
or GND, V
CC
= 5.5V, outputs unloaded.
5. I
CCOP
measured at 10MHz for the 80C286-10/883 and 12.5MHz for the 80C286-12/883. V
IN
= 2.4V or 0.4V, V
CC
= 5.5V, outputs unloaded.
6. I
SH
should be measured after raising V
IN
to V
CC
and then lowering to 0V on pins 53 and 54.
131
80C286/883
TABLE 2. 80C286/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Datasheet Waveforms, Unless Otherwise Noted. Device
Guaranteed and 100% Tested.
PARAMETER
SYMBOL
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
80C286/883
UNITS
10MHz
12.5MHz
MIN
MAX
MIN
MAX
System Clock
(CLK) Period
1
V
CC
= 4.5V and 5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
50
-
40
-
ns
System Clock
(CLK) Low Time
2
V
CC
= 4.5V and 5.5V
at 1.0V
9, 10, 11
-55
o
C
T
A
+125
o
C
12
-
11
-
ns
System Clock (CLK)
High Time
3
V
CC
= 4.5V and 5.5V
at 3.6V
9, 10, 11
-55
o
C
T
A
+125
o
C
16
-
13
-
ns
Asynchronous Inputs
SETUP Time
(Note 1)
4
V
CC
= 4.5V
and 5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
20
-
15
-
ns
Asynchronous Inputs
HOLD Time
(Note 1)
5
V
CC
= 4.5V
and 5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
20
-
15
-
ns
RESET SETUP Time
6
V
CC
= 4.5V
and 5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
19
-
10
-
ns
RESET HOLD Time
7
V
CC
= 4.5V
and 5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
0
-
0
-
ns
Read Data
SETUP Time
8
V
CC
= 4.5V
and 5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
8
-
5
-
ns
Read Data
HOLD Time
9
V
CC
= 4.5V
and 5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
4
-
4
-
ns
READY SETUP Time
10
V
CC
= 4.5V
and 5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
26
-
20
-
ns
READY HOLD Time
11
V
CC
= 4.5V
and 5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
25
-
20
-
ns
Status/PEACK Active
Delay, (Note 4)
12A
V
CC
= 4.5V and
5.5V, C
L
= 100pF
I
L
= |2mA|
9, 10, 11
-55
o
C
T
A
+125
o
C
1
22
1
21
ns
Status/PEACK
Inactive Delay
(Note 3)
12B
V
CC
= 4.5V and
5.5V, C
L
= 100pF
I
L
= |2mA|
9, 10, 11
-55
o
C
T
A
+125
o
C
1
30
1
24
ns
Address Valid
Delay (Note 2)
13
V
CC
= 4.5V and
5.5V, C
L
= 100pF
I
L
= |2mA|
9, 10, 11
-55
o
C
T
A
+125
o
C
1
35
1
32
ns
Write Data
Valid Delay, (Note 2)
14
V
CC
= 4.5V and
5.5V, C
L
= 100pF
I
L
= |2mA|
9, 10, 11
-55
o
C
T
A
+125
o
C
0
40
0
31
ns
132
80C286/883
HLDA Valid Delay
(Note 5)
15
V
CC
= 4.5V and
5.5V, C
L
= 100pF
IL = |2mA|
9, 10, 11
-55
o
C
T
A
+125
o
C
0
47
0
25
ns
NOTES:
1. Asynchronous inputs are INTR, NMI, HOLD, PEREQ, ERROR, and BUSY. This specification is given only for testing purposes, to assure
recognition at a specific CLK edge.
2. Delay from 1.0V on the CLK to 0.8V or 2.0V.
3. Delay from 1.0V on the CLK to 0.8V for Min (HOLD time) and to 2.0V for Max (inactive delay).
4. Delay from 1.0V on the CLK to 2.0V for Min (HOLD time) and to 0.8V for Max (active delay).
5. Delay from 1.0V on the CLK to 2.0V.
TABLE 3. 80C286/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
80C286/883
UNITS
10MHz
12.5MHz
MIN
MAX
MIN
MAX
CLK Input Capacitance
C
CLK
FREQ = 1MHz
5
T
A
= +25
o
C
-
10
-
10
pF
Other Input Capacitance
C
IN
FREQ = 1MH
5
T
A
= +25
o
C
-
10
-
10
pF
I/O Capacitance
C
I/O
FREQ = 1MH
5
T
A
= +25
o
C
-
10
-
10
pF
Address/Status/Data
Float Delay
15
1, 3, 4, 5
-55
o
C
T
A
+125
o
C
0
47
0
32
ns
Address Valid to Status
SETUP Time
19
I
L
= | 2.0mA|
1, 2, 5
-55
o
C
T
A
+125
o
C
27
-
20
-
ns
NOTES:
1. Output Load: C
L
= 100pF.
2. Delay measured from address either reaching 0.8V or 2.0V (valid) to status going active reaching 0.8V or status going inactive reaching
2.0V.
3. Delay from 1.0V on the CLK to Float (no current drive) condition.
4. I
L
= -6mA (V
OH
to Float), I
L
= 8mA (V
OL
to Float).
5. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are char-
acterized upon initial design and after major process and/or design changes.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
Initial Test
100%/5004
-
Interim Test
100%/5004
1, 7, 9
PDA
100%
1
Final Test
100%
2, 3, 8A, 8B, 10, 11
Group A
-
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group C & D
Samples/5005
1, 7, 9
TABLE 2. 80C286/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Datasheet Waveforms, Unless Otherwise Noted. Device
Guaranteed and 100% Tested.
PARAMETER
SYMBOL
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
80C286/883
UNITS
10MHz
12.5MHz
MIN
MAX
MIN
MAX
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