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Datasheet: 24502BVA (Intersil Corporation)

1024 x 4 CMOS RAM

 

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Intersil Corporation
6-1
March 1997
HM-6514
1024 x 4 CMOS RAM
Features
Low Power Standby . . . . . . . . . . . . . . . . . . . 125
W Max
Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max
Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
TTL Compatible Input/Output
Common Data Input/Output
Three-State Output
Standard JEDEC Pinout
Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max
18 Pin Package for High Density
On-Chip Address Register
Gated Inputs - No Pull Up or Pull Down Resistors
Required
Description
The HM-6514 is a 1024 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. The device utilizes
synchronous circuitry to achieve high performance and low
power operation.
On-chip latches are provided for addresses allowing efficient
interfacing with microprocessor systems. The data output
can be forced to a high impedance state for use in expanded
memory arrays.
Gated inputs allow lower operating current and also elimi-
nate the need for pull up or pull down resistors. The
HM-6514 is a fully static RAM and may be maintained in any
state for an indefinite period of time.
Data retention supply voltage and supply current are guaran-
teed over temperature.
Ordering Information
120ns
200ns
300ns
TEMPERATURE RANGE
PACKAGE
PKG. NO.
HM3-6514S-9
HM3-6514B-9
HM3-6514-9
-40
o
C to +85
o
C
PDIP
E18.3
HM1-6514S-9
HM1-6514B-9
HM1-6514-9
-40
o
C to +85
o
C
CERDIP
F18.3
24502BVA
-
-
-
JAN#
F18.3
8102402VA
8102404VA
8102406VA
-
SMD#
F18.3
-
-
-
-40
o
C to +85
o
C
CLCC
J18.B
-
-
HM4-6514-B
-55
o
C to +125
o
C
J18.B
Pinouts
HM-6514 (PDIP, CERDIP)
TOP VIEW
HM-6514 (CLCC)
TOP VIEW
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
V
CC
A8
A9
DQ0
DQ1
DQ2
DQ3
A7
W
A6
A5
A4
A3
A0
A1
E
A2
GND
PIN
DESCRIPTION
A
Address Input
E
Chip Enable
W
Write Enable
D
Data Input
Q
Data Output
3
4
5
6
7
8
9
10
11
2
1
17
13
12
16
15
14
A3
A4
A0
A1
A2
GND
DQ3
W
E
A7
A6
DQ0
DQ1
A9
DQ2
A8
A5
V
CC
18
File Number
2995.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
6-2
Functional Diagram
64
A
6
6
4
L
G
A
A9
A8
A7
A6
A5
A4
64 x 64
MATRIX
G
A2
A1
A0
A3
E
W
LATCHED
ADDRESS
REGISTER
A
4
4
A
L
16 16 16
16
1 OF 4
DQ
LATCHED
ADDRESS
REGISTER
GATED
ROW
DECODER
LSB
LSB
GATED
COLUMN
I/O SELECT
HM-6514
6-3
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to V
CC
+0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Ranges:
HM-6514S-9, HM-6514B-9, HM-6514-9 . . . . . . . . -40
o
C to +85
o
C
HM-6514B-8, HM-6514-8 . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Thermal Resistance (Typical)
JA
JC
CERDIP Package . . . . . . . . . . . . . . . .
75
o
C/W
15
o
C/W
PDIP Package . . . . . . . . . . . . . . . . . . .
75
o
C/W
N/A
CLCC Package . . . . . . . . . . . . . . . . . .
90
o
C/W
33
o
C/W
Maximum Storage Temperature Range . . . . . . . . .-65
o
C to +150
o
C
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300
o
C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
V
CC
= 5V
10%; T
A
= -40
o
C to +85
o
C (HM-6514S-9, HM-6514B-9, HM-6514-9)
T
A
= -55
o
C to +125
o
C (HM-6514B-8, HM-6514-8)
SYMBOL
PARAMETER
LIMITS
UNITS
TEST CONDITIONS
MIN
MAX
ICCSB
Standby Supply Current
HM-6514-9
-
25
A
IO = 0mA, E = V
CC
-0.3V, V
CC
= 5.5V
HM-6514-8
-
50
A
ICCOP
Operating Supply Current (Note 1)
-
7
mA
E = 1MHz, IO = 0mA, VI = GND,
V
CC
= 5.5V
ICCDR
Data Retention Supply
Current
HM-6514-9
-
15
A
IO = 0mA, V
CC
= 2.0V, E = V
CC
HM-6514-8
-
25
A
VCCDR
Data Retention Supply Voltage
2.0
-
V
II
Input Leakage Current
-1.0
+1.0
A
VI = V
CC
or GND, V
CC
= 5.5V
IIOZ
Input/Output Leakage Current
-1.0
+1.0
A
VIO = V
CC
or GND, V
CC
= 5.5V
VIL
Input Low Voltage
-0.3
0.8
V
V
CC
= 4.5V
VIH
Input High Voltage
V
CC
-2.0
V
CC
+0.3
V
V
CC
= 5.5V
VOL
Output Low Voltage
-
0.4
V
IO = 2.0mA, V
CC
= 4.5V
VOH1
Output High Voltage
2.4
-
V
IO = -1.0mA, V
CC
= 4.5V
VOH2
Output High Voltage (Note 2)
V
CC
-0.4
-
V
IO = -100
A, V
CC
= 4.5V
Capacitance
T
A
= +25
o
C
SYMBOL
PARAMETER
MAX
UNITS
TEST CONDITIONS
CI
Input Capacitance (Note 2)
8
pF
f = 1MHz, All measurements are
referenced to device GND
CIO
Input/Output Capacitance (Note 2)
10
pF
NOTES:
1. Typical derating 5mA/MHz increase in ICCOP.
2. Tested at initial design and after major design changes.
HM-6514
6-4
AC Electrical Specifications
V
CC
= 5V
10%; T
A
= -40
o
C to +85
o
C (HM-6514S-9, HM-6514B-9, HM-6514-9)
T
A
= -55
o
C to +125
o
C (HM-6514B-8, HM-6514-8)
SYMBOL
PARAMETER
LIMITS
UNITS
TEST
CONDITIONS
HM-6514S-9
HM-6514B-9
HM-6514-9
MIN
MAX
MIN
MAX
MIN
MAX
(1)
TELQV
Chip Enable Access Time
-
120
-
220
-
300
ns
(Notes 1, 3)
(2)
TAVQV
Address Access Time
-
120
-
220
-
320
ns
(Notes 1, 3, 4)
(3)
TELQX
Chip Enable Output Enable
Time
5
-
5
-
5
-
ns
(Notes 2, 3)
(4)
TEHQZ
Chip Enable Output Disable
Time
-
50
-
80
-
100
ns
(Notes 2, 3)
(5)
TELEH
Chip Enable Pulse Negative
Width
120
-
200
-
300
-
ns
(Notes 1, 3)
(6)
TEHEL
Chip Enable Pulse Positive
Width
50
-
90
-
120
-
ns
(Notes 1, 3)
(7)
TAVEL
Address Setup Time
0
-
20
-
20
-
ns
(Notes 1, 3)
(8)
TELAX
Address Hold Time
40
-
50
-
50
-
ns
(Notes 1, 3)
(9)
TWLWH
Write Enable Pulse Width
120
-
200
-
300
-
ns
(Notes 1, 3)
(10)
TWLEH
Chip Enable Write Pulse
Setup Time
120
-
200
-
300
-
ns
(Notes 1, 3)
(11)
TELWH
Chip Enable Write Pulse Hold
Time
120
-
200
-
300
-
ns
(Notes 1, 3)
(12)
TDVWH
Data Setup Time
50
-
120
-
200
-
ns
(Notes 1, 3)
(13)
TWHDX
Data Hold Time
0
-
0
-
0
-
ns
(Notes 1, 3)
(14)
TWLDV
Write Data Delay Time
70
-
80
-
100
-
ns
(Notes 1, 3)
(15)
TWLEL
Early Output High-Z Time
0
-
0
-
0
-
ns
(Notes 1, 3)
(16)
TEHWH
Late Output High-Z Time
0
-
0
-
0
-
ns
(Notes 1, 3)
(17)
TELEL
Read or Write Cycle Time
170
-
290
-
420
-
-
(Notes 1, 3)
NOTES:
1. Input pulse levels: 0.8V to V
CC
- 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
1 TTL gate equivalent, C
L
= 50pF (min) - for C
L
greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
3. V
CC
= 4.5V and 5.5V.
4. TAVQV = TELQV + TAVEL.
HM-6514
6-5
Timing Waveforms
The address information is latched in the on-chip registers
on the falling edge of E (T = 0). Minimum address set up and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time (T = 1) the output becomes
enabled, but data is not valid until during time (T = 2). W
must remain high throughout the read cycle. After the output
data has been read, E may return high (T = 3). This will dis-
able the output buffer and all inputs, and ready the RAM for
the next memory cycle (T = 4).
(8)
(7) TAVEL
(6)
(4) TEHQZ
HIGH Z
VALID DATA OUT
(6)
HIGH Z
TAVEL
(7)
-1
TIME
0
1
2
3
4
5
REFERENCE
(2) TAVQV
(17) TELEL
TELAX
NEXT ADD
TEHEL
(2) TAVQY
TEHEL
(5) TELEH
(1) TELQV
(3) TELQX
DQ
W
E
A
FIGURE 1. READ CYCLE
VALID ADD
TRUTH TABLE
TIME
REFERENCE
INPUTS
DATA I/O
DQ
FUNCTION
E
W
A
-1
H
X
X
Z
Memory Disabled
0
H
V
Z
Cycle Begins, Addresses are Latched
1
L
H
X
X
Output Enabled
2
L
H
X
V
Output Valid
3
H
X
V
Read Accomplished
4
H
X
X
Z
Prepare for Next Cycle (Same as -1)
5
H
V
Z
Cycle Ends, Next Cycle Begins (Same as 0)
HM-6514
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