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Datasheet: I960 (Intel Corporation)

Rp/rd I/o Processor At 3.3 Volts

 

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Intel Corporation

Document Outline

INTEL CORPORATION, 1997
September, 1997
Order Number: 273001-002
ADVANCE INFORMATION
i960
RP/RD I/O PROCESSOR AT 3.3 VOLTS
33 MHz, 3.3 Volt Version (80960RP 33/3.3)
66 MHz, 3.3 Volt Version (80960RD 66/3.3) - Clock Doubled 80960JF Core
Complies with PCI Local Bus Specification Revision 2.1
5 Volt PCI Signalling Environment
s
High Performance 80960JF Core
-- Sustained One Instruction/Clock
Execution
-- 4 Kbyte Two-Way Set-Associative
Instruction Cache
-- 2 Kbyte Direct-Mapped Data Cache
-- Sixteen 32-Bit Global Registers
-- Sixteen 32-Bit Local Registers
-- Programmable Bus Widths:
8-, 16-, 32-Bit
-- 1 Kbyte Internal Data RAM
-- Local Register Cache
(Eight Available Stack Frames)
-- Two 32-Bit On-Chip Timer Units
s
PCI-to-PCI Bridge Unit
-- Primary and Secondary PCI Interfaces
-- Two 64-Byte Posting Buffers
-- Delayed and Posted Transaction
Support
-- Forwards Memory, I/O, Configuration
Commands from PCI Bus to PCI Bus
s
Two Address Translation Units
-- Connects Local Bus to PCI Buses
-- Inbound/Outbound Address Translation
Support
-- Direct Outbound Addressing Support
s
Messaging Unit
-- Four Message Registers
-- Two Doorbell Registers
-- Four Circular Queues
-- 1004 Index Registers
s
Memory Controller
-- 256 Mbytes of 32- or 36-Bit DRAM
-- Interleaved or Non-Interleaved DRAM
-- Fast Page-Mode DRAM Support
-- Extended Data Out and Burst
-- Extended Data Out DRAM Support
-- Two Independent Banks for SRAM / ROM
/ Flash (16 Mbytes/Bank; 8- or 32-Bit)
s
DMA Controller
-- Three Independent Channels
-- PCI Memory Controller Interface
-- 32-Bit Local Bus Addressing
-- 64-Bit PCI Bus Addressing
-- Independent Interface to Primary and
Secondary PCI Buses
-- 132 Mbyte/sec Burst Transfers to PCI
and Local Buses
-- Direct Addressing to and from PCI
Buses
-- Unaligned Transfers Supported in
Hardware
-- Two Channels Dedicated to Primary
PCI Bus
-- One Channel Dedicated to Secondary
PCI Bus
s
I/O APIC Bus Interface Unit
-- Multiprocessor Interrupt Management
for Intel Architecture CPUs
(Pentium
and Pentium
Pro
Processors)
-- Dynamic Interrupt Distribution
-- Multiple I/O Subsystem Support
s
I
2
C Bus Interface Unit
-- Serial Bus
-- Master/Slave Capabilities
-- System Management Functions
s
Secondary PCI Arbitration Unit
-- Supports Six Secondary PCI Devices
-- Multi-priority Arbitration Algorithm
-- External Arbitration Support Mode
s
Private PCI Device Support
s
SuperBGA* Package
-- 352 Ball-Grid Array (HL-PBGA)
Information in this document is provided in connection with Intel products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel
disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or
warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright
or other intellectual property right. Intel products are not intended for use in medical, life saving, or life
sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
*Third-party brands and names are the property of their respective owners.
Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature, may be obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect IL 60056-764
or call 1-800-548-4725
INTEL CORPORATION, 1997
i960
Rx I/O Processor at 3.3 V
iii
1.0 ABOUT THIS DOCUMENT ....................................................................................................................... 1
1.1 Solutions960
Program ...................................................................................................................... 1
1.2 Terminology ........................................................................................................................................ 1
1.3 Additional Information Sources ........................................................................................................... 1
2.0 FUNCTIONAL OVERVIEW ....................................................................................................................... 2
2.1 Key Functional Units ........................................................................................................................... 3
2.1.1 PCI-to-PCI Bridge Unit ............................................................................................................. 3
2.1.2 Private PCI Device Support ..................................................................................................... 3
2.1.3 DMA Controller ........................................................................................................................ 3
2.1.4 Address Translation Unit .......................................................................................................... 3
2.1.5 Messaging Unit ........................................................................................................................ 3
2.1.6 Memory Controller ................................................................................................................... 3
2.1.7 I2C Bus Interface Unit .............................................................................................................. 3
2.1.8 I/O APIC Bus Interface Unit ..................................................................................................... 3
2.1.9 Secondary PCI Arbitration Unit ................................................................................................ 4
2.2 i960 Core Features (80960JF) ........................................................................................................... 4
2.2.1 Burst Bus ................................................................................................................................. 5
2.2.2 Timer Unit ................................................................................................................................ 5
2.2.3 Priority Interrupt Controller ....................................................................................................... 5
2.2.4 Faults and Debugging .............................................................................................................. 5
2.2.5 On-Chip Cache and Data RAM ................................................................................................ 5
2.2.6 Local Register Cache ............................................................................................................... 5
2.2.7 Test Features ........................................................................................................................... 5
2.2.8 Memory-Mapped Control Registers ......................................................................................... 6
2.2.9 Instructions, Data Types and Memory Addressing Modes ...................................................... 6
3.0 PACKAGE INFORMATION ....................................................................................................................... 8
3.1 Package Introduction .......................................................................................................................... 8
3.1.1 Functional Signal Definitions .................................................................................................... 8
3.1.2 352-Lead HL-PBGA Package ................................................................................................ 21
3.2 Package Thermal Specifications ...................................................................................................... 31
3.2.1 Thermal Specifications ........................................................................................................... 31
3.2.1.1 Ambient Temperature ............................................................................................... 31
3.2.1.2 Case Temperature .................................................................................................... 31
3.2.1.3 Thermal Resistance .................................................................................................. 31
3.2.2 Thermal Analysis ................................................................................................................... 32
3.3 Sources for Heatsinks and Accessories ........................................................................................... 33
4.0 ELECTRICAL SPECIFICATIONS ........................................................................................................... 34
4.1 Absolute Maximum Ratings .............................................................................................................. 34
4.2 V
CC5
Pin Requirements (V
DIFF
) ........................................................................................................ 34
4.3 Targeted DC Specifications .............................................................................................................. 35
4.4 Targeted AC Specifications .............................................................................................................. 37
4.4.1 Relative Output Timings ......................................................................................................... 39
4.4.2 Memory Controller Relative Output Timings .......................................................................... 39
4.4.3 Boundary Scan Test Signal Timings ...................................................................................... 42
4.4.4 APIC Bus Interface Signal Timings ........................................................................................ 42
4.4.5 I2C Interface Signal Timings .................................................................................................. 43
4.5 AC Test Conditions ........................................................................................................................... 44
4.6 AC Timing Waveforms ...................................................................................................................... 44
4.7 Memory Controller Output Timing Waveforms ................................................................................. 48
5.0 BUS FUNCTIONAL WAVEFORMS ........................................................................................................ 55
6.0 DEVICE IDENTIFICATION ON RESET ................................................................................................... 64
i960
Rx I/O Processor at 3.3 V
iv
FIGURES
Figure 1.
i960
Rx I/O Processor at 3.3 V Functional Block Diagram .......................................................... 2
Figure 2.
80960JF Core Block Diagram ........................................................................................................ 4
Figure 3.
352L HL-PBGA Package Diagram (Top and Side View) ............................................................. 21
Figure 4.
352L HL-PBGA Package Diagram (Bottom View) ....................................................................... 22
Figure 5.
Thermocouple Attachment - No Heat Sink .................................................................................. 31
Figure 6.
Thermocouple Attachment - With Heat Sink ................................................................................ 31
Figure 7.
VCC5 Current-Limiting Resistor ................................................................................................... 34
Figure 8.
AC Test Load ............................................................................................................................... 44
Figure 9.
S_CLK, TCLK Waveform ............................................................................................................. 44
Figure 10. T
OV
Output Delay Waveform ....................................................................................................... 45
Figure 11. T
OF
Output Float Waveform ......................................................................................................... 45
Figure 12. T
IS
and T
IH
Input Setup and Hold Waveform ............................................................................... 46
Figure 13. T
LXL
and T
LXA
Relative Timings Waveform ................................................................................. 46
Figure 14. DT/R# and DEN# Timings Waveform .......................................................................................... 47
Figure 15. I
2
C Interface Signal Timings ........................................................................................................ 47
Figure 16. Fast Page-Mode Read Access, Non-Interleaved, 2,1,1,1 Wait State, 32-Bit 80960 Local Bus ... 48
Figure 17. Fast Page-Mode Write Access, Non-Interleaved, 2,1,1,1 Wait States, 32-Bit 80960 Local Bus . 49
Figure 18. FPM DRAM System Read Access, Interleaved, 2,0,0,0 Wait States .......................................... 50
Figure 19. FPM DRAM System Write Access, Interleaved, 1,0,0,0 Wait States ........................................... 51
Figure 20. EDO DRAM, Read Cycle ............................................................................................................. 52
Figure 21. EDO DRAM, Write Cycle ............................................................................................................. 52
Figure 22. BEDO DRAM, Read Cycle ........................................................................................................... 53
Figure 23. BEDO DRAM, Write Cycle ........................................................................................................... 53
Figure 24. 32-Bit Bus, SRAM Read Accesses with 0 Wait States ................................................................ 54
Figure 25. 32-Bit Bus, SRAM Write Accesses with 0 Wait States ................................................................ 54
Figure 26. Non-Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus .............. 55
Figure 27. Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus ...................... 56
Figure 28. Burst Write Transactions with 2,1,1,1 Wait States, 32-Bit 80960 Local Bus ................................ 57
Figure 29. Burst Read and Write Transactions without Wait States, 8-Bit 80960 Local Bus ........................ 58
Figure 30. Burst Read and Write Transactions with 1, 0 Wait States and Extra Tr State on Read,
16-Bit 80960 Local Bus ................................................................................................................ 59
Figure 31. Bus Transactions Generated by Double Word Read Bus Request, Misaligned One Byte From
Quad Word Boundary, 32-Bit 80960 Local Bus ........................................................................... 60
Figure 32. HOLD/HOLDA Waveform For Bus Arbitration ............................................................................. 61
Figure 33. 80960 Core Cold Reset Waveform .............................................................................................. 62
Figure 34. 80960 Local Bus Warm Reset Waveform .................................................................................... 63
TABLES
Table 1.
Related Documentation ................................................................................................................. 1
Table 2.
80960Rx Instruction Set ................................................................................................................ 7
Table 3.
Signal Type Definition .................................................................................................................... 8
Table 4.
Signal Descriptions ........................................................................................................................ 9
Table 5.
Power Requirement, Processor Control and Test Signal Descriptions ....................................... 13
Table 6.
Interrupt Unit Signal Descriptions .................................................................................... ............ 14
Table 7.
PCI Signal Descriptions ............................................................................................... ................ 15
Table 8.
Memory Controller Signal Descriptions ....................................................................................... 18
Table 9.
DMA, APIC, I
2
C Units Signal Descriptions .................................................................................. 19
Table 10.
Clock Signal ................................................................................................................................. 20
Table 11.
ICE Signal Descriptions ............................................................................................................... 20
Table 12.
352-Lead HL-PBGA Package -- Signal Name Order
(Sheet 1 of 4) ........................................... 23
Table 13.
352-Lead HL-PBGA Pinout -- Ballpad Number Order (Sheet 1 of 4) ......................................... 27
Table 14.
352-Lead HL-PBGA Package Thermal Characteristics ............................................................... 32
Table 15.
Heatsink Information .................................................................................................................... 33
Table 16.
Operating Conditions ................................................................................................................... 34
Table 17.
V
DIFF
Specification for Dual Power Supply Requirements (3.3 V, 5 V) ....................................... 34
Table 18.
DC Characteristics ....................................................................................................................... 35
Table 19.
I
CC
Characteristics ....................................................................................................................... 36
Table 20.
Input Clock Timings ..................................................................................................................... 37
Table 21.
Synchronous Output Timings ...................................................................................................... 37
Table 22.
Synchronous Input Timings ......................................................................................................... 38
Table 23.
Relative Output Timings .............................................................................................................. 39
Table 24.
Fast Page Mode Non-interleaved DRAM Output Timings ........................................................... 39
Table 25.
Fast Page Mode Interleaved DRAM Output Timings ................................................................... 40
Table 26.
EDO DRAM Output Timings ........................................................................................................ 40
Table 27.
BEDO DRAM Output Timings ...................................................................................................... 41
Table 28.
SRAM/ROM Output Timings ........................................................................................................ 41
Table 29.
Boundary Scan Test Signal Timings ............................................................................................ 42
Table 30.
APIC Bus Interface Signal Timings .............................................................................................. 42
Table 31.
I2C Interface Signal Timings ........................................................................................................ 43
Table 32.
Processor Device ID Register - PDIDR ...................................................................................... 64
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