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Datasheet: I82371MX (Intel Corporation)

Intel 430mx Pciset 82371mx Mobile Pci I/o Ide Xcelerator (mpiix)

 

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Intel Corporation

Document Outline

PRELIMINARY
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright,
for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make changes to those
specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
COPYRIGHT INTEL CORPORATION, 1996
April 1996
Order Number: 290525-001
Provides a Bridge Between the PCI Bus
and Extended I/O Bus
PCI Bus; 2533 MHz
Extended I/O Bus; 7.58.33 MHz
System Power Management (Intel SMM
Support)
Programmable System Management
Interrupt (SMI)--Hardware/Software
Events, EXTSMI#
Programmable CPU Clock Control
(STPCLK#) with Auto Clock Throttle
Peripheral Device Power
Management (Local Standby)
Suspend State Support (Suspend-to-
DRAM and Suspend-to-Disk)
Enhanced DMA Functions
Two 8237 DMA Controllers
Fast Type F DMA
Compatible DMA Transfers
PC/PCI DMA Expansion for Docking
Support
Fast IDE Interface
PIO Mode 4 Transfers
2x16-Bit Posted Write Buffer and
1x32-Bit Read Prefetch Buffer
Plug-n-Play Port for Motherboard
Devices
3 Steerable DMA Channels
1 Steerable Interrupt Line (Plus 2
Steerable PCI Interrupts)
1 Programmable Chip Select
Functionality of One 82C54 Timer
System Timer
Refresh Request
Speaker Tone Output
Functionality of Two 82C59 Interrupt
Controllers
14 Interrupts Supported
Independently Programmable for
Edge/Level Sensitivity
X-Bus Peripheral Support
Chip Select Decode
Controls Lower X-Bus Data Byte
Transceiver
Non-Maskable Interrupts (NMI)
PCI System Error Reporting
NAND Tree for Board-Level ATE Testing
176-Pin TQFP
The 82371MX PCI I/O IDE Xcelerator (MPIIX) provides the bridge between the PCI bus and the ISA-like
Extended I/O expansion bus. In addition, the 82371MX has an IDE interface that supports two IDE devices
providing an interface for IDE hard disks and CD ROMs. The MPIIX integrates many common I/O functions
found in ISA based PC systems--a seven-channel DMA controller, two 82C59 interrupt controllers, an 8254
timer/counter, Intel SMM power management support, and control logic for NMI generation. Chip select decoding
is provided for BIOS, real time clock, and keyboard controller. Edge/Level interrupts and interrupt steering are
supported for PCI plug and play compatibility.
The MPIIX also provides the Extended I/O Bus for a direct connection to Super I/O devices providing a complete
PC-compatible I/O solution. MPIIX also provides support for the "Mobile PC/PCI" DMA Expansion protocol that
enables the implementation of Docking Stations with full ISA and PCI capability without running the full ISA bus
across the docking connector. For motherboard Plug-n-Play compatibility, the 82371MX also provides three
steerable DMA channels, up to three steerable interrupt lines, and a programmable chip select. The interrupt
lines can be routed to any of the available ISA interrupts.
The MPIIX's power management function supports SMI# interrupt sources, extensive clock control (including
Auto Clock Throttling), peripheral power idle detection with access traps, system Suspend-to-DRAM and
Suspend-to-Disk.
INTEL 430MX PCISET
82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)
82371MX (MPIIX)
2
PRELIMINARY
PCI
Bus
Interface
E xtended
B us
In terface
A nd
M otherb oard
In terface
Interrupt
Timers/
Counters
DMA
AD[31:0]
C/BE[3:0]#
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#
SERR#
PAR
IDSEL
M IR Q
M D R Q 0
M DA K0#
INTR
NMI
IRQ(15,14,11:9,7:3,1)
DA CK 2#
TC
D A [2:0]/S A [2:0]
D D [15:8]/S A [15:8]/S D [15:8]
M E M R #
M E M W #
IO C H RD Y
S YSC LK
IO R #
IO W #
ZERO W S#
SPKR
FER R #
IG N N E#
OSC
IRQ12/M
IRQ8#
Test
TESTIN#
PIRQ [A ,B ]#
SMI#
STPCLK#
EXTSMI#
System
Power
Mgmt
PHOLD
PHOLDA#
System
Clocks
and
Reset
PWROK
CPURST
PCIRST#
RSTDRV
INIT
IDE
Interface
D D [7:0]/S D [7:0]
M
U
X
D C S1#/SA 7
D C S3#/SA 6
DIOR#
DIOW#
IORDY
DO E#/SM OUT5
M
U
X
ALTA20M
B IOS CS#
DR EQ 2
G N T[A ,B]#
REQ [A,B]#
CLK R U N#
S US TA T#
SY SAC T#
SRBTN#
B ATLO W #
R SM RST#
CO M RI #
PC S# o r SA 17
R TC C S# or SA16
KB CS#
RTCALE/SM O UT4
M
U
X
HC LK
H CLK0
PC IC LK
PC IC LKO
R TCC LK
RTC CLK O
SMO UT5
SMO UT4
SMO UT[3:0]
SD IR
M D R Q 2/EX TEVN T #
M D A K 2#/PA D#
M
U
X
EXTEVNT#
PAD#
MPIX_BLK
82371MX MPIIX Block Diagram
82371MX (MPIIX)
3
PRELIMINARY
CONTENTS
1.0. ARCHITECTURE OVERVIEW...................................................................................................................9
2.0 SIGNAL DESCRIPTION.............................................................................................................................11
2.1. PCI Interface Signals.............................................................................................................................. 11
2.2. IDE Interface Signals.............................................................................................................................. 13
2.3. Extended I/O Bus Signals ...................................................................................................................... 14
2.4. Motherboard I/O Device Interface Signals ............................................................................................ 15
2.5. DMA Signals ...........................................................................................................................................17
2.6. Interrupt Controller Signals .................................................................................................................... 17
2.7. System Power Management ( SMM) Signals ........................................................................................ 19
2.8. System Clock And Reset Signals ..........................................................................................................20
2.9. Test Signals ............................................................................................................................................21
3.0. REGISTER DESCRIPTION.......................................................................................................................22
3.1. Register Access ......................................................................................................................................22
3.2. PCI Configuration Registers .................................................................................................................. 27
3.2.1. VID--VENDOR IDENTIFICATION REGISTER ............................................................................27
3.2.2. DID--DEVICE IDENTIFICATION REGISTER ..............................................................................27
3.2.3. COM--COMMAND REGISTER .....................................................................................................28
3.2.4. DS--DEVICE STATUS REGISTER .............................................................................................. 28
3.2.5. RID--REVISION IDENTIFICATION REGISTER ..........................................................................29
3.2.6. CLASSC--CLASS CODE REGISTER .......................................................................................... 29
3.2.7. HEDT--HEADER TYPE REGISTER ............................................................................................ 30
3.2.8. SPPE--SERIAL & PARALLEL PORT ENABLE REGISTER ...................................................... 30
3.2.9. ECRT-- EXTENDED I/O CONTROLLER RECOVERY TIMER REGISTER ............................. 31
3.2.10. BIOSE -- BIOS ENABLE REGISTER ......................................................................................... 31
3.2.11. FDCE--FDC ENABLE REGISTER ............................................................................................. 32
3.2.12. PIRQRC [A,B]--PIRQX ROUTE CONTROL REGISTERS ........................................................ 33
3.2.13. MSTAT--MISCELLANEOUS STATUS REGISTER ..................................................................33
3.2.14. IDETIM--IDE TIMING REGISTER .............................................................................................. 34
3.2.15. MIRQRC--MOTHERBOARD DEVICE IRQ ROUTE CONTROL REGISTER .......................... 35
3.2.16. MDMARC[2:0]
MOTHERBOARD DEVICE DMA ROUTE CONTROL REGISTERS ............36
3.2.17. AUDIOE--AUDIO ENABLE REGISTER .................................................................................... 37
3.2.18. DMADS--DMA CH[7:5] DATA SIZE REGISTER .......................................................................37
3.2.19. PCIDMAE--PCI DMA ENABLE REGISTER ..............................................................................37
3.2.20. PCIDMA[A,B]
PCI DMA AND PCI DMA EXPANSION REGISTER .......................................38
3.2.21. PMAC[1:0]--PROGRAMMABLE MEMORY ADDRESS CONTROL REGISTERS .................39
3.2.22. PMAM[1:0]--PROGRAMMABLE MEMORY ADDRESS MASK REGISTERS ......................... 40
3.2.23. PARE--PROGRAMMABLE ADDRESS RANGE ENABLE REGISTER ...................................40
3.2.24. PCSC--PROGRAMMABLE CHIP SELECT CONTROL REGISTER .......................................41
82371MX (MPIIX)
4
PRELIMINARY
3.2.25. PAC[5:1]--PROGRAMMABLE ADDRESS CONTROL REGISTER .........................................41
3.2.26. PAMA--PROGRAMMABLE ADDRESS MASK A REGISTER ..................................................41
3.2.27. PAMB--PROGRAMMABLE ADDRESS MASK B REGISTER ..................................................42
3.2.28. IOCA--I/O CONFIGURATION ADDRESS REGISTER .............................................................42
3.2.29. PAMC--PROGRAMMABLE ADDRESS MASK C REGISTER .................................................43
3.2.30. PADE[2:0]--PERIPHERAL ACCESS DETECT ENABLE REGISTERS ..................................43
3.2.31. LTADEV3--Local Trap Address for Device 3 Register .............................................................44
3.2.32. LTMDEV3--Local Trap Mask for Device 3 Register ...................................................................44
3.2.33. LTSMIE--Local Trap SMI Enable Register ................................................................................44
3.2.34. LTSMIS--Local Trap SMI Status Register ..................................................................................45
3.2.35. LSBSMIE--Local Standby SMI Enable Register ........................................................................45
3.2.36. LSBTRE--Local Standby Timer Reload Enable Register ..........................................................46
3.2.37. LSBSMIS--Local Standby SMI Status Register ..........................................................................47
3.2.38. LSTBTIDE--Local Standby IDE Timer Register .........................................................................47
3.2.39. LSBTAUD--Local Standby Audio Timer Register ......................................................................48
3.2.40. LSBTCOM--Local Standby COM Timer Register .......................................................................48
3.2.41. LSBTDEV1--Local Standby Device 1 Timer Register ...............................................................48
3.2.42. LSBTDEV2--Local Standby Device 2 Timer Register ...............................................................49
3.2.43. LSBTDEV3--Local Standby Device 3 Timer Register ...............................................................49
3.2.44. SESMIT--Software/EXTSMI# SMI Delay Timer Register ..........................................................49
3.2.45. SUSSMIT--Suspend SMI Delay Timer Register ........................................................................50
3.2.46. GSBTMR--Global Standby Timer Register .................................................................................50
3.2.47. CLKTHSBYT -- Clock Throttle Standby Timer Register ............................................................50
3.2.48. SYSMGNTC--System Management Control Register ...............................................................51
3.2.49. SYSSMIE--System SMI Enable Register ...................................................................................51
3.2.50. MISCSMIE--Misc SMI Enable Register ......................................................................................52
3.2.51. GSMIE--Global SMI Enable Register ..........................................................................................52
3.2.52. SYSSMIS--System SMI STATUS Register ................................................................................53
3.2.53. MISCSMIS--Miscellaneous SMI STATUS Register ...................................................................53
3.2.54. GSMIS -- Global SMI STATUS Register ....................................................................................54
3.2.55. SUSRSMC1--Suspend/Resume Control 1 Register ..................................................................54
3.2.56. SUSRSMC2--Suspend/Resume Control 2 Register ..................................................................55
3.2.57. SMOUTC--SMOUT Control Register ..........................................................................................55
3.2.58. SYSEVNTE0--System EVENT Enable 0 Register ....................................................................56
3.2.59. SYSEVNTE1--System EVENT Enable 1 Register ....................................................................56
3.2.60. SYSEVNTE2--System EVENT Enable 2 Register ....................................................................57
3.2.61. BSTCLKT -- Burst Count Timer Register ....................................................................................57
3.2.62. CLKC--Clock Control Register ....................................................................................................58
3.2.63. STPCLKLT--STPCLK# Low Timer Register ..............................................................................58
3.2.64. STPCLKHT--STPCLK# High Timer Count .................................................................................59
3.2.65. STPBRKE0--Stop Break Event Enable 0 Register ....................................................................59
3.2.66. STPBRKE1--Stop Break Event Enable 1 Register ....................................................................60
82371MX (MPIIX)
5
PRELIMINARY
3.2.67. STPBRKE2--Stop Break Event Enable 2 Register ....................................................................60
3.2.68. SHDW--Shadow Register Access Port ...................................................................................... 61
3.2.69. BSTCLKEE[6:0]--Burst Clock Event Enable Registers ............................................................. 63
3.2.70. CLKTHLBRKEE[6:0]--Clock Throttle Break Event Enable Registers ......................................64
3.3. ISA Compatible Registers ...................................................................................................................... 64
3.3.1. DMA REGISTERS........................................................................................................................... 64
3.3.1.1. DCOM--DMA Command Register .......................................................................................... 65
3.3.1.2. DCM--DMA Channel Mode Register ..................................................................................... 65
3.3.1.3. DR--DMA Request Register ...................................................................................................66
3.3.1.4. Mask Register--Write Single Mask Bit ................................................................................... 66
3.3.1.5. Mask Register--Write All Mask Bits ........................................................................................ 67
3.3.1.6. DS--DMA Status Register .......................................................................................................68
3.3.1.7. DMA Base and Current Address Registers (8237 Compatible Segment) ............................ 68
3.3.1.8. DMA Base and Current Byte/Word Count Registers (Compatible Segment) ....................... 69
3.3.1.9. DMA Memory Low Page Registers ......................................................................................... 69
3.3.1.10. DMA Clear Byte Pointer Register .......................................................................................... 70
3.3.1.11. DMC--DMA Master Clear Register ...................................................................................... 70
3.3.1.12. DCLM--DMA Clear Mask Register ....................................................................................... 70
3.3.2. TIMER/COUNTER REGISTERS ...................................................................................................71
3.3.2.1. TCW--Timer Control Word Register ....................................................................................... 71
3.3.2.2. Interval Timer Status Byte Format Register ............................................................................73
3.3.2.3. Counter Access Ports Register ............................................................................................... 73
3.3.3. INTERRUPT CONTROLLER REGISTERS .................................................................................. 74
3.3.3.1. ICW1--Initialization Command Word 1 Register ...................................................................74
3.3.3.2. ICW2--Initialization Command Word 2 Register ...................................................................75
3.3.3.3. ICW3--Initialization Command Word 3 Register ...................................................................75
3.3.3.4. ICW3--Initialization Command Word 3 Register ...................................................................75
3.3.3.5. ICW4--Initialization Command Word 4 Register ...................................................................76
3.3.3.6. OCW1--Operational Control Word 1 Register .......................................................................76
3.3.3.7. OCW2--Operational Control Word 2 Register .......................................................................77
3.3.3.8. OCW3--Operational Control Word 3 Register .......................................................................77
3.3.3.9. ELCR1--Edge/Level Triggered Register ................................................................................78
3.3.3.10. ELCR2--Edge/Level Triggered Register .............................................................................79
3.3.4. RESET EXTENDED I/O-BUS IRQ12 AND IRQ1 REGISTER ..................................................... 79
3.3.5. NMI REGISTERS ............................................................................................................................ 80
3.3.5.1. NMISC--NMI Status and Control Register .............................................................................80
3.3.5.2. NMI Enable and Real-Time Clock Address Register ............................................................. 81
3.3.5.3. Coprocessor Error Register .....................................................................................................81
3.3.5.4. RC--Reset Control Register ...................................................................................................81
3.3.5.5. Port 92 Register ........................................................................................................................ 82
3.4. Advanced Power Management Registers ............................................................................................ 83
3.4.1. APMC--ADVANCED POWER MANAGEMENT CONTROL PORT ...........................................83
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