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Datasheet: F28F010-150 (Intel Corporation)

1024K (128K x 8) CMOS FLASH MEMORY

 

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Intel Corporation
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
November 1995
COPYRIGHT
INTEL CORPORATION 1995
Order Number 290207-010
28F010
1024K (128K x 8) CMOS FLASH MEMORY
Y
Flash Electrical Chip-Erase
1 Second Typical Chip-Erase
Y
Quick Pulse Programming Algorithm
10 ms Typical Byte-Program
2 Second Chip-Program
Y
100 000 Erase Program Cycles
Y
12 0V
g
5% V
PP
Y
High-Performance Read
65 ns Maximum Access Time
Y
CMOS Low Power Consumption
10 mA Typical Active Current
50 mA Typical Standby Current
0 Watts Data Retention Power
Y
Integrated Program Erase Stop Timer
Y
Command Register Architecture for
Microprocessor Microcontroller
Compatible Write Interface
Y
Noise Immunity Features
g
10% V
CC
Tolerance
Maximum Latch-Up Immunity
through EPI Processing
Y
ETOX
TM
Nonvolatile Flash Technology
EPROM-Compatible Process Base
High-Volume Manufacturing
Experience
Y
JEDEC-Standard Pinouts
32-Pin Plastic Dip
32-Lead PLCC
32-Lead TSOP
(See Packaging Spec Order
231369)
Y
Extended Temperature Options
Intel's 28F010 CMOS flash memory offers the most cost-effective and reliable alternative for read write
random access nonvolatile memory The 28F010 adds electrical chip-erasure and reprogramming to familiar
EPROM technology Memory contents can be rewritten in a test socket in a PROM-programmer socket on-
board during subassembly test in-system during final test and in-system after-sale The 28F010 increases
memory flexibility while contributing to time and cost savings
The 28F010 is a 1024 kilobit nonvolatile memory organized as 131 072 bytes of 8 bits Intel's 28F010 is
offered in 32-pin plastic dip or 32-lead PLCC and TSOP packages Pin assignments conform to JEDEC
standards for byte-wide EPROMs
Extended erase and program cycling capability is designed into Intel's ETOX (EPROM Tunnel Oxide) process
technology Advanced oxide processing an optimized tunneling structure and lower electric field combine to
extend reliable cycling beyond that of traditional EEPROMs With the 12 0V V
PP
supply the 28F010 performs
100 000 erase and program cycles well within the time limits of the Quick Pulse Programming and Quick Erase
algorithms
Intel's 28F010 employs advanced CMOS circuitry for systems requiring high-performance access speeds low
power consumption and immunity to noise Its 65 nanosecond access time provides no-WAIT-state perform-
ance for a wide range of microprocessors and microcontrollers Maximum standby current of 100 mA trans-
lates into power savings when the device is deselected Finally the highest degree of latch-up protection is
achieved through Intel's unique EPI processing Prevention of latch-up is provided for stresses up to 100 mA
on address and data pins from b1V to V
CC
a
1V
With Intel's ETOX process base the 28F010 builds on years of EPROM experience to yield the highest levels
of quality reliability and cost-effectiveness
28F010
290207 1
Figure 1 28F010 Block Diagram
Table 1 Pin Description
Symbol
Type
Name and Function
A
0
A
16
INPUT
ADDRESS INPUTS
for memory addresses Addresses are internally
latched during a write cycle
DQ
0
DQ
7
INPUT OUTPUT
DATA INPUT OUTPUT
Inputs data during memory write cycles
outputs data during memory read cycles The data pins are active high
and float to tri-state OFF when the chip is deselected or the outputs
are disabled Data is internally latched during a write cycle
CE
INPUT
CHIP ENABLE
Activates the device's control logic input buffers
decoders and sense amplifiers CE
is active low CE
high
deselects the memory device and reduces power consumption to
standby levels
OE
INPUT
OUTPUT ENABLE
Gates the devices output through the data buffers
during a read cycle OE
is active low
WE
INPUT
WRITE ENABLE
Controls writes to the control register and the array
Write enable is active low Addresses are latched on the falling edge
and data is latched on the rising edge of the WE
pulse
Note
With V
PP
s
6 5V memory contents cannot be altered
V
PP
ERASE PROGRAM POWER SUPPLY
for writing the command
register erasing the entire array or programming bytes in the array
V
CC
DEVICE POWER SUPPLY
(5V
g
10%)
V
SS
GROUND
NC
NO INTERNAL CONNECTION
to device Pin may be driven or left
floating
2
28F010
28F010
290207 2
290207 3
290207 17
290207 18
Figure 2 28F010 Pin Configurations
3
28F010
APPLICATIONS
The 28F010 flash memory provides nonvolatility
along with the capability to perform over 100 000
electrical chip-erasure reprogram cycles These fea-
tures make the 28F010 an innovative alternative to
disk
EEPROM
and battery-backed static RAM
Where periodic updates of code and data-tables are
required the 28F010's reprogrammability and non-
volatility make it the obvious and ideal replacement
for EPROM
Primary applications and operating systems stored
in flash eliminate the slow disk-to-DRAM download
process This results in dramatic enhancement of
performance and substantial reduction of power
consumption
a consideration particularly impor-
tant in portable equipment Flash memory increases
flexibility with electrical chip erasure and in-system
update capability of operating systems and applica-
tion code With updatable code system manufactur-
ers can easily accommodate last-minute changes as
revisions are made
In diskless workstations and terminals network traf-
fic reduces to a minimum and systems are instant-
on Reliability exceeds that of electromechanical
media Often in these environments power interrup-
tions force extended re-boot periods for all net-
worked terminals This mishap is no longer an issue
if boot code operating systems communication pro-
tocols and primary applications are flash-resident in
each terminal
For embedded systems that rely on dynamic RAM
disk for main system memory or nonvolatile backup
storage the 28F010 flash memory offers a solid
state alternative in a minimal form factor
The
28F010 provides higher performance lower power
consumption instant-on capability and allows an
``execute in place'' memory hierarchy for code and
data table reading Additionally the flash memory is
more rugged and reliable in harsh environments
where extreme temperatures and shock can cause
disk-based systems to fail
The need for code updates pervades all phases of a
system's life
from prototyping to system manufac-
ture to after-sale service The electrical chip-erasure
and reprogramming ability of the 28F010 allows in-
circuit alterability this eliminates unnecessary han-
dling and less-reliable socketed connections while
adding greater test manufacture and update flexi-
bility
Material and labor costs associated with code
changes increases at higher levels of system inte-
gration
the most costly being code updates after
sale Code ``bugs'' or the desire to augment system
functionality prompt after-sale code updates Field
revisions to EPROM-based code requires the re-
moval of EPROM components or entire boards With
the 28F010 code updates are implemented locally
via an edge-connector or remotely over a commun-
cation link
For systems currently using a high-density static
RAM battery configuration for data accumulation
flash memory's inherent nonvolatility eliminates the
need for battery backup The concern for battery
failure no longer exists an important consideration
for portable equipment and medical instruments
both requiring continuous performance In addition
flash memory offers a considerable cost advantage
over static RAM
Flash memory's electrical chip erasure byte pro-
grammability and complete nonvolatility fit well with
data accumulation and recording needs Electrical
chip-erasure gives the designer a ``blank slate'' in
which to log or record data Data can be periodically
off-loaded for analysis and the flash memory erased
producing a new ``blank slate''
A high degree of on-chip feature integration simpli-
fies memory-to-processor interfacing Figure 4 de-
picts two 28F010s tied to the 80C186 system bus
The 28F010's architecture minimizes interface cir-
cuitry needed for complete in-circuit updates of
memory contents
The outstanding feature of the TSOP (Thin Small
Outline Package) is the 1 2 mm thickness With stan-
dard and reverse pin configurations TSOP reduces
the number of board layers and overall volume nec-
essary to layout multiple 28F010s TSOP is particu-
larly suited for portable equipment and applications
requiring large amounts of flash memory Figure 3
illustrates the TSOP Serpentine layout
With cost-effective in-system reprogramming ex-
tended cycling capability
and true nonvolatility
the 28F010 offers advantages to the alternatives
EPROMs EEPROMs battery backed static RAM
or disk
EPROM-compatible read specifications
straight-forward interfacing and in-circuit alterability
offers designers unlimited flexibility to meet the high
standards of today's designs
4
28F010
Figure 3 TSOP Serpentine Layout
290207
2
1
5
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