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Datasheet: IA8044-PLC40I-01 (InnovASIC, Inc.)

0.3-6VDC; 2W; 8-bit Control Unit; SDLC Communications Controller

 

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InnovASIC, Inc.
IA8044/IA8344
Data Sheet
SDLC COMMUNICATIONS CONTROLLER

Copyright
2003
ENG210010112-00
www.innovasic.com
innov
ASIC
Customer Support:
The End of Obsolescence
TM
Page 1 of 49
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FEATURES
Form, Fit, and Function Compatible with the Intel
8044/8344
Packaging options available: 40 Pin Plastic Dual In-Line Package (PDIP),
44 Pin Plastic Leaded Chip Carrier (PLCC)
8-Bit Control Unit
8-Bit Arithmetic-Logic Unit with 16-Bit multiplication and division
12 MHz clock
Four 8-Bit Input / Output ports
Two 16-Bit Timer/Counters
Serial Interface Unit with SDLC/HDLC compatibility
2.4 Mbps maximum serial data rate
Two Level Priority Interrupt System
5 Interrupt Sources
Internal Clock prescaler and Phase generator
192 Bytes of Read/Write Data Memory Space
64kB External Program Memory Space
64kB External Data Memory Space
4kB Internal ROM (IA8044 only)
IA8044/IA8344 Variants
IA8044
4kB internal ROM with R0117 version 2.3 firmware, 192 byte internal RAM,
64kB external program and data space.
IA8344 192 byte internal RAM, 64kB external program and data space.
The IA8044/IA8344 is a "plug-and-play" drop-in replacement for the original IC. InnovASIC
produces replacement ICs using its MILES
TM
, or Managed IC Lifetime Extension System, cloning
technology. This technology produces replacement ICs far more complex than "emulation" while
ensuring they are compatible with the original IC. MILES
TM
captures the design of a clone so it can
be produced even as silicon technology advances. MILES
TM
also verifies the clone against the
original IC so that even the "undocumented features" are duplicated. This data sheet documents all
necessary engineering information about the IA8044/IA8344 including functional and I/O
descriptions, electrical characteristics, and applicable timing.
innov
ASIC
IA8044/IA8344
Data Sheet
SDLC COMMUNICATIONS CONTROLLER

Copyright
2003
ENG210010112-00
www.innovasic.com
innov
ASIC
Customer Support:
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TM
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Package Pinout
(6)
P1.5
(1)
P1.0
(2)
P1.1
(3)
P1.2
(4)
P1.3
(5)
P1.4
(7)
(RTS) P1.6
(8)
(9)
RST
(10)
(11)
(12)
(INT0) P3.2
(13)
(INT1) P3.3
(14)
40 Pin DIP
IA8X44
P0.7 (AD7)
EA
ALE
PSEN
(20)
VSS
(15)
(SCLK/T1) P3.5
(16)
(WR) P3.6
(17)
(RD) P3.7
(18)
XTAL2
(19)
XTAL1
(21)
(22)
(23)
(24)
P2.1 (A9)
P2.0 (A8)
(40)
(39)
(38)
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
(28)
(27)
(26)
(25)
(T0) P3.4
P2.3 (A11)
P2.2 (A10)
P2.5 (A13)
P2.4 (A12)
P2.7 (A15)
P2.6 (A14)
P0.5 (AD5)
P0.6 (AD6)
P0.3 (AD3)
P0.4 (AD4)
P0.1 (AD1)
P0.2 (AD2)
VCC
P0.0 (AD0)
(CTS) P1.7
(RXD) P3.0
(TXD) P3.1
P1.3
P1.4
P3.6
P2.6
44 Pin LCC
IA8X44
(12)
N.C.
(7)
P1.5
(8)
P1.6
(9)
P1.7
(10)
RST/VPD
(11)
P3.0
(13)
P3.1
(14)
P3.2
(15)
P3.3
(16)
P3.4
(17)
P3.5
P0.4
ALE
N.C.
EA
P0.6
P0.5
XTAL2
P3.7
(6)
(5)
(4)
(3)
(2)
(1)
(44)
(43)
(42)
P0.1
(41)
P0.2
(40)
P0.3
(34)
(39)
(38)
(37)
(36)
(35)
(33)
(32)
(31)
(30)
(29)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
VCC
P0.0
P1.0
N.C.
P1.2
P1.1
VSS
XTAL1
P2.0
N.C.
P2.2
P2.1
P2.4
P2.3
P2.5
P2.7
PSEN
P0.7
DESCRIPTION
The IA8044/IA8344 is a form, fit and function compatible part to the Intel
8X44 SDLC
communications controller. The IA8044/IA8344 is a Fast Single-Chip 8-Bit Microcontroller with an
integrated SDLC/HDLC serial interface controller. The IA8044/IA8344 is a fully functional 8-Bit
Embedded Controller that executes all ASM51 instructions and has the same instruction set as the
Intel 80C51. The IA8044/IA8344 can access the instructions from two types of program memory,
serves software and hardware interrupts, provides an interface for serial communications and a timer
system. The IA8044/IA8344 is fully compatible with the Intel
8X44 series. The functional block
diagram is shown below.
IA8044/IA8344
Data Sheet
SDLC COMMUNICATIONS CONTROLLER

Copyright
2003
ENG210010112-00
www.innovasic.com
innov
ASIC
Customer Support:
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TM
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Functional Block Diagram
192x8Dual Port
RAM
C8051
CPU
Interrupts
Timers
Port 0
ADDR/DATA/IO
Port 2
ADDR/DATA/IO
Port 1
SPCL FUNC/IO
Port 3
SPCL FUNC/IO
SIU
Control
Address/Data
Clock Gen.
& Timing
XTAL
Reset
Memory
Control
I/O for Memory, SIU, DMA, Interrupts, Timers
IA8044/IA8344
Data Sheet
SDLC COMMUNICATIONS CONTROLLER

Copyright
2003
ENG210010112-00
www.innovasic.com
innov
ASIC
Customer Support:
The End of Obsolescence
TM
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I/O Characteristics
The table below describes the I/O characteristics for each signal on the IC. The signal names
correspond to the signal names on the pinout diagrams provided. The table below provides the I/O
description of the IA8044 and the IA8344.
Name
Type
Description
RST
I
Reset. This pin when held high for two machine cycles while
the oscillator is running will cause the chip to reset.
ALE
O
Address Latch Enable. Used to latch the address on the falling
edge for external memory accesses.
PSEN
O
Program Store Enable. When low acts as an output enable for
external program memory.
EA
I
External Access. When held low EA will cause the
IA8044/IA8344 to fetch instructions from external memory.
P0.7 P0.0
I/O
Port 0. 8 bit I/O port and low order multiplexed address/data
byte for external accesses.
P1.7 P1.0
I/O
Port 1. 8-bit I/O port. Two bits have alternate functions, P1.6
(RTS) and P1.7 (CTS).
P2.7 P2.0
I/O
Port 2. 8-bit I/O port. It also functions as the high order
address byte during external accesses.
P3.7 P3.0
I/O
Port 3. 8-bit I/O port. Port 3 bits also have alternate functions
as described below.
P3.0 RXD. Receive data input for SIU or direction control
for P3.1 dependent upon datalink configuration.
P3.1 TXD. Transmit data output for SIU or data
input/output dependent upon datalink configuration. Also
enables diagnostic mode when cleared.
P3.2 INT0. Interrupt 0 input or gate control input for counter
0.
P3.3 INT1. Interrupt 1 input or gate control input for counter
1.
P3.4 T0. Input to counter 0.
P3.5 SCLK/T1. SCLK input to SIU or input to counter 1.
P3.6 WR. External memory write signal.
P3.7 RD. External memory read signal.
XTAL1
I
Crystal Input 1. Connect to VSS when external clock is used on
XTAL2. May be connected to a crystal (with XTAL2), or may
be driven directly with a clock source (XTAL2 not connected).
XTAL2
O
Crystal Input 2. May be connected to a crystal (with XTAL1),
or may be driven directly with an inverted clock source (XTAL1
tied to ground).
VSS
P
Ground.
VCC
P
+5V power.
IA8044/IA8344
Data Sheet
SDLC COMMUNICATIONS CONTROLLER

Copyright
2003
ENG210010112-00
www.innovasic.com
innov
ASIC
Customer Support:
The End of Obsolescence
TM
Page 5 of 49
1-888-824-4184

Memory Organization
Program Memory
Program Memory includes interrupt and Reset vectors. The interrupt vectors are spaced at 8-
byte intervals, starting from 0003H for External Interrupt 0.
Reset Vectors
These locations may be used for program code, if the corresponding interrupts are not used
(disabled). The Program Memory space is 64K, from 0000H to FFFFH. The lowest 4K of program
code (0000H to 0FFFH) can be fetched from external or internal Program Memory. This selection is
made by strapping pin `EA' (External Address) to GND or VCC. If during reset, `EA' is held low,
all the program code is fetched from external memory. If, during reset, `EA' is held high, the lowest
4K of program code (0000H to 0FFFH) is fetched from internal memory (ROM). Program
memory addresses above 4K (0FFFH) will cause the program code to be fetched from external
memory regardless of the setting of `EA'.
Data Memory
External Data Memory
The IA8044/IA8344 Microcontroller core incorporates the Harvard architecture, with separate
code and data spaces. The code from external memory is fetched by `psen' strobe, while data
is read from RAM by bit 7 of P3 (read strobe) and written to RAM by bit 6 of P3 (write strobe). The
External Data Memory space is active only by addressing through use of the MOVX instruction and
the 16-bit Data Pointer Register (DPTR). A smaller subset of external data memory (8 bit
addressing) may be accessed by using the MOVX instruction with register indexed addressing.

Internal Data Memory
The Internal Data Memory address is always 1 byte wide. The memory space is 192 bytes
large (00H to BFH), and can be accessed by either direct or indirect addressing. The Special
Function Registers occupy the upper 128 bytes. This SFR area is available only by direct
addressing. Internal memory that overlaps the SFR address space is only accessible by indirect
addressing.
Location
Service
0003H
External Interrupt 0
000BH
Timer 0 overflow
0013H
External Interrupt 1
001BH
Timer 1 overflow
0023H
SIU Interrupt
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