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Datasheet: ILC5061AM-44 (Impala Linear Corporation)

SOT-23 POWER SUPPLY RESET MONITOR

 

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Impala Linear Corporation
ILC5061
SOT-23 Power Supply reset Monitor
Impala Linear Corporation
Impala Linear Corporation
1
(408) 574-3939
www.impalalinear.com
June 1999
ILC5061 1.7
All-CMOS Monitor circuits in a 3-lead SOT-23 package offer the
best performance in power consumption and accuracy.
The ILC5061 comes in a series of 1% accurate trip voltages to
fit most microprocessor applications. Even though its output
can sink 2mA, the device draws only 1A in normal operation.
Additionally, a built-in hysteresis of 5% of detect voltage
simplifies system design.
All-CMOS design in SOT-23 and SOT-89 package
1% precision in Reset Detection
Only 1A of Iq
2mA of sink current capability
Built-in hysteresis of 5% of detection voltage
Voltage options of 2.6, 2.9, 3.1, 4.4, and 4.6V fit most
supervisory applications
Microprocessor reset circuits
Memory battery back-up circuitry
Power-on reset circuits
Portable and battery powered electronics
V
IN
V
SS
V
R E F
V
OUT
Ordering Information*
ILC5061AM-26
2.6V+1% Monitor in SOT-23
ILC5061AM-27
2.7V+1% Monitor in SOT-23
ILC5061AM-28
2.8V+1% Monitor in SOT-23
ILC5061AM-29
2.9V+1% Monitor in SOT-23
ILC5061AM-31
3.1V+1% Monitor in SOT-23
ILC5061AM-44
4.4V+1% Monitor in SOT-23
ILC5061AM-46
4.6V+1% Monitor in SOT-23
ILC5061M-26
2.6V+2% Monitor in SOT-23
ILC5061M-27
2.7V+2% Monitor in SOT-23
ILC5061M-28
2.8V+2% Monitor in SOT-23
ILC5061M-29
2.9V+2% Monitor in SOT-23
ILC5061M-31
3.1V+2% Monitor in SOT-23
ILC5061M-44
4.4V+2% Monitor in SOT-23
ILC5061M-46
4.6V+2% Monitor in SOT-23
* Standard product offering comes in tape and reel,
quantity 3000 per reel orientation right
V
OUT
V
S S
V
I N
SOT -23
(TOP VI EW)
1
3
2
N-Channel Open Drain Output
General Description
Features
Applications
Block Diagram
Pin Package Configurations
Impala Linear Corporation
2
(408) 574-3939
www.impalalinear.com
June 1999
ILC5061 1.7
Parameter
Symbol
Conditions
Min
Type
Max
Units
Detect Fail Voltage
V
DF
A grade
V
DF
X 0.99
V
DF
V
DF
X 1.01
V
Detect Fail Voltage
V
DF
Standard grade
V
DF
X 0.99
V
DF
V
DF
X 1.02
V
Hysteresis Range
V
HYS
V
DF
X 0.02
V
DF
X 0.05
V
DF
X 0.08
V


Supply Current

I
SS
V
IN
= 1.5V
V
IN
= 2.0V
V
IN
= 3.0V
V
IN
= 4.0V
V
IN
= 5.0V
0.9
1.0
1.3
1.6
2.0
2.6
3.0
3.4
3.8
4.2
!
!
"
A
Operating Voltage
V
IN
V
DF
= 2.1~ 6.0V
1.5
10.0
V


Output Current

I
OUT

N-ch
V
DS
= 0.5V
V
IN
= 1.0V
V
IN
= 2.0V
V
IN
= 3.0V
V
IN
= 4.0V
V
IN
= 5.0V
P-ch
V
DS
= 2.1V
V
IN
= 8V
2.2
7.7
10.1
11.5
13.0
-10

mA
Temperature
Characteristics
#
V
DF
/(
#
T
opr
!
V
DF
)
30
o
C <T
opr
<80
o
C
+100
Ppm/
o
C
Delay Time Release
Voltage Output
Inversion)
T
DLY
(V
DR
V
OUT
inversion)
0.2
ms
Note:
1. An additional resistor between the V
IN
pin and supply voltage may cause deterioration of the characteristics due to increasing V
DR
.
Parameter
Symbol
Ratings
Units
Input Voltages
V
IN
12
V
Output Current
I
OUT
50
mA
Output Voltages
V
OUT
V
SS
-0.3~+V
IN
+03
V
Continuous Total SOT-23
Power Dissipation
P
d
150
mW
Operation Ambient temperature
T
opr
-30~+80
o
C
Storage Temperature
T
stg
-40~+125
o
C
SOT-23 Power Supply reset Monitor
Absolute Maximum Ratings (T
A
=25

C)
Electrical Characteristics (T
A
=25

C)
Impala Linear Corporation
3
(408) 574-3939
www.impalalinear.com
June 1999
ILC5061 1.7
The following designators 1~6 refer to the timing diagram below.
1. While the input voltage (V
IN
) is higher than the detect volt-
age (V
DF
), the V
OUT
output pin is at high impedance state.
2. When the input VIN voltage falls lower than V
DF
, V
OUT
drops near to ground voltage
3. If the input voltage further decreases below the mini-
mum operating voltage (V
MIN
), the V
OUT
output becomes
unstable. In this condition, if the V
OUT
pin is pulled up,
V
OUT
indicates the V
IN
voltage.
4. During an increase of the input voltage from the V
SS
voltage, V
OUT
is not stable in the voltage below the V
MIN
.
Exceeding that level, the output stays at the ground level
(V
SS
) between the minimum operating voltage (V
MIN
) and
the detect release voltage (V
DR
).
5. If the input voltage increases more than V
DR
, then the
V
OUT
output pin is at high impedance state.
6. The difference between VDR and VDF is the hysteresis
in the system.
6
5
4
3
1
2
INPUT VOLTAGE (V
IN
)
DETECT RELEASE VOLTAGE (V
DR
)
DETECT FAIL VOLTAGE (V
DF
)
MINIMUM OPERATING VOLTAGE (V
MIN
)
GROUND VOLTAGE (V
SS
)
OUTPUT VOLTAGE (V
OUT
)
GROUND VOLTAGE (V
SS
)
SOT-23 Power Supply reset Monitor
Functional Description
Timing Diagram
Impala Linear Corporation
4
(408) 574-3939
www.impalalinear.com
June 1999
ILC5061 1.7
OUTPUT V OLTA GE V
O UT
(V)
0
60
O
U
T
P
UT
CUR
RE
NT
I
OU
T
(mA
)
1
80
10
0
2
V
I N
=4.0V
OUTPUT VOLTAGE vs OUTPUT CURRENT
ILC5061
OU TPU T VOLTAGE V
O UT
(V)
0. 0
400
O
U
T
P
UT
CUR
RE
NT
I
OU
T
(
A
)
800
1. 0
1000
600
200
0.0
0.6
OUTPUT VOLTAGE vs OUTPUT CURRENT
ILC5061
3
4
3.5V
V
I N
=0.8V
INPUT VOLTAGE V
I N
(V )
0
2. 0
I
DD
(
A
)
4. 0
10
3. 0
1. 0
0
5
I
D D
vs INPUT VOLTAGE *
ILC5061
T
o pr
=80C
25C
20
30
40
50
70
3.0V
2.5V
2.0V
1.5V
0. 2
0. 4
0. 8
V
I N
=0.7V
INPUT VOLTAGE V
I N
(V )
0
10
O
U
T
P
U
T
C
URRE
N
T
I
OU
T
(mA
)
20
5
25
15
5
0
3
V
DS
=0.5V
OUTPUT CURRENT vs INPUT VOLTAGE
ILC5061
T
o pr
=30C
25C
1
2
3
4
6
7
8
9
-30C
1
2
4
80C
* A spike of to 1
A may appear as Vin crosses V
DR
or V
DF
V
DS = 0.5V
SOT-23 Power Supply reset Monitor
Typical Performance Characteristics - general conditions for all curves
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