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Datasheet: V104YLFT (Integrated Circuit Systems)

10 BIT LVDS RECEIVER FOR VIDEO

 

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Integrated Circuit Systems

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V104
V104 Datasheet
1
1/12/05
Revision 1.6
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
10 B
IT
LVDS R
ECEIVER
FOR
V
IDEO
PRELIMINARY
General Description
The V104 10 Bit LVDS Receiver for Video is designed
to support video data transmission between display
engines and video processing engines for television
and projector applications. The V104 supports up to
WXGA resolutions for Plasma, Rear Projection, Front
Projection, CRT and LCD applications.
The V104 converts the 6 LVDS (Low Voltage
Differential Signaling) video data stream pairs to 35
CMOS/TTL data bits with a rising or falling edge clock.
The clock edge selection is performed using a
dedicated pin.
In conjunction with the V103 transmitter, the V104 can
transmit 10 bits per color (R, G, B) along with 5 bits of
control and timing data (HSYNC, VSYNC, DE, CNTL1,
CNTL2) over a low EMI, low bus width connection
including connectors and standard LVDS cabling.
Features
Pin & function compatible with the THC63LVD104A
Wide pixel clock range: 8 - 90 MHz
Supports resolutions from 480p to WXGA
Internal PLL does not require external loop filter
Clock edge selection for TTL alignment selectable
Power down mode
Single 3.3V supply
Low power consumption CMOS design
64-pin TQFP lead free package
Block Diagram
Serial to
Parallel
PLL
CLKOUT
TEST
RA+/-
RB+/-
RC+/-
RD+/-
RE+/-
RCLK+/-
(8 to 90 MHz)
PD
OE
R/F
LVDS Input
CMOS/TTL Input
CMOS/TTL Output
RA6-RA0
RB6-RB0
RC6-RC0
RD6-RD0
RE6-RE0
7
7
7
7
7
10 B
IT
LVDS R
ECEIVER
FOR
V
IDEO
V104
V104 Datasheet
2
1/12/05
Revision 1.6
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
PRELIMINARY
Pin Assignment
Pin Descriptions
Pin
Number
Pin
Name
Pin Type
Pin Description
50, 49
RA+, RA-
LVDS IN
LVDS Data In
52, 51
RB+, RB-
LVDS IN
LVDS Data In
55, 54
RC+, RC-
LVDS IN
LVDS Data In
60, 59
RD+, RD-
LVDS IN
LVDS Data In
62, 61
RE+, RE-
LVDS IN
LVDS Data In
57, 56
RCLK+, RCLK-
LVDS IN
LVDS Clock In
40, 41, 42, 43,
45, 46, 47
RA6 ~ RA0
OUT
CMOS/TTL Data Outputs
32, 33, 34, 35,
36, 38, 39
RB6 ~ RB0
OUT
CMOS/TTL Data Outputs
22, 24, 25, 26,
27, 28, 29
RC6 ~ RC0
OUT
CMOS/TTL Data Outputs
14, 15, 17, 18,
19, 20, 21
RD6 ~ RD0
OUT
CMOS/TTL Data Outputs
12
1
11
2
10
GND
3
9
TEST
4
5
6
7
8
16
15
14
13
64-pin TQFP
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
PD
OE
RE6
RE5
RE4
R/F
VCC
RE3
RE2
RE1
RE0
RD6
RD5
GND
RB5
17
18
19
20
21
22
23
24
25
26
27
28
RD
4
32
31
30
29
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
RD
3
RD
2
RD1
RD
0
RC
6
VC
C
RC
5
RC
4
RC
3
RC
2
RC
1
RC
0
GN
D
CLK
O
UT
RB
6
RB4
RB3
RB2
VCC
RB1
RB0
RA6
RA5
RA4
RA3
GND
RA2
RA1
RA0
VCC
RA-
RA+
RB
-
RB
+
LV
C
C
RC
-
RC
+
RC
LK-
RC
LK+
LG
ND
RD
-
RD
+
RE
-
RE
+
PGN
D
PV
CC
10 B
IT
LVDS R
ECEIVER
FOR
V
IDEO
V104
V104 Datasheet
3
1/12/05
Revision 1.6
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
PRELIMINARY
**Rxn
x = A, B, C, D, E
n = 0, 1, 2, 3, 4, 5, 6
6, 7, 8, 10, 11,
12, 13
RE6 ~ RE0
OUT
CMOS/TTL Data Outputs.
2
TEST
IN
Not used. Tie LOW.
3
PD
IN
HIGH: normal operation; LOW: Power down (all outputs are "L").
4
OE
IN
HIGH: Output enable (normal operation); LOW: Output disable (all outputs
are high impedance).
5
R/F
IN
Output Clock triggering edge select. High: Rising edge; Low: Falling edge.
9, 23, 37, 48
VCC
Power
Power supply pins for TTL outputs and digital circuitry.
31
CLKOUT
OUT
Clock out.
1, 16, 30, 44
GND
Ground
Ground pins for TTL outputs and digital circuitry.
53
LVCC
Power
Power supply pins for LVDS inputs.
58
LGND
Ground
Ground pins for LVDS inputs.
64
PVCC
Power
Power supply pin for PLL circuitry.
63
PGND
Ground
Ground pin for PLL circuitry.
Pin
Number
Pin
Name
Pin Type
Pin Description
PD
R/F
OE
Data Outputs (Rxn)
CLKOUT
0
0
0
High impedance
High impedance
0
0
1
All 0
Fixed Low
0
1
0
High impedance
High impedance
0
1
1
All 0
Fixed Low
1
0
0
High impedance
High impedance
1
0
1
Data Out
Latches output data on falling edge
1
1
0
High impedance
High impedance
1
1
1
Data Out
Latches output data on rising edge
10 B
IT
LVDS R
ECEIVER
FOR
V
IDEO
V104
V104 Datasheet
4
1/12/05
Revision 1.6
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
PRELIMINARY
External Components
The V104 requires no external components.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the V104. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
Item
Rating
Supply Voltage, VCC
-0.3 V to +4.0 V
CMOS/TTL Input Voltage
-0.3 V to VCC+0.3 V
CMOS/TTL Output Voltage
-0.3 V to VCC+0.3 V
LVDS Receiver Input Voltage
-0.3 V to VCC+0.3 V
Output Current
-30 mA to 30 mA
Storage Temperature
-55 to +125
C
Junction Temperature
125
C
Soldering Temperature (10 seconds)
260
C
Maximum Power Dissipation @ +25C
1.0 W
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
0
+70
C
Power Supply Voltage (measured in respect to GND)
+3.0
+3.6
V
10 B
IT
LVDS R
ECEIVER
FOR
V
IDEO
V104
V104 Datasheet
5
1/12/05
Revision 1.6
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
PRELIMINARY
Electrical Characteristics
VDD=3.3 V 10%,
Ambient temperature 0 to +70
C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
CMOS/TTL DC Specifications
Input High Voltage
V
IH
2.00
VCC
V
Input Low Voltage
V
IL
GND
0.80
V
Output High Voltage
V
OH
I
OH
= -4 mA (data)
I
OH
= -8 mA (clock)
2.4
V
Output Low Voltage
V
OL
I
OH
= -4 mA (data)
I
OH
= -8 mA (clock)
0.4
V
Input Current
I
INC
0V<VIN<VCC
10
A
LVDS Receiver DC Specifications
Differential Input High Threshold
V
TH
V
OC
= 1.2 V
100
mV
Differential Input Low Threshold
V
TL
V
OC
= 1.2 V
-100
mV
Input Current
I
INL
V
IN
= 2.4 V / 0V
V
IN
= 3.6 V
20
A
Parameter
Symbol
Conditions
Typ.
Max.
Units
Supply Current
Receiver Supply Current (Gray Scale
Pattern)
I
RCCG
f
CLKOUT
= 90 MHz
C
L
=8 pF,
V
CC
= 3.3 V
70
mA
Receiver Supply Current (Checker
Pattern)
I
RCCW
f
CLKOUT
= 90 MHz
C
L
=8 pF,
V
CC
= 3.3 V
112
mA
Receiver Power Down Supply Current
I
RCCS
PD = L
10
A
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