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Datasheet: V103YLF (Integrated Circuit Systems)

TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO

 

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Integrated Circuit Systems

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V103
V103 Datasheet
1
11/23/06
Revision 2.0
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst. com
T
RIPLE
10-B
IT
LVDS T
RANSMITTER
FOR
V
IDEO
General Description
The V103 LVDS display interface transmitter is
primarily designed to support pixel data transmission
between a video processing engine and a digital video
display. The data rate supports up to SXGA+
resolutions and can be used in Plasma, Rear Projector,
Front Projector, CRT and LCD display applications. It
can also be used in other high-bandwidth parallel data
applications and provides a low EMI interconnect over
a low cost, low bus width cable up to several meters in
length.
The V103 converts 35 bits of CMOS/TTL data, clocked
on the rising or falling edge of an input clock
(selectable), into six LVDS (Low Voltage Differential
Signaling) serial data stream pairs. In video
applications the 35 bits is normally divided into 10 bits
for each R, G and B channel and 5 control bits.
When combined with the V104 LVDS display interface
receiver, the V103 + V104 combination provides a
35-bit wide, 90 MHz transport. The rate of each LVDS
channel is 630 Mbps for a 90MHz data input clock, 945
Mbps for 135MHz.
Features
Pin compatible with THine THC63LVD103
Wide pixel clock range: 8 - 135 MHz
Supports a wide range of video and graphics modes
including VGA, SVGA, XGA, SXGA, SXGA+, NTSC,
PAL, SDTV, and HDTV up to 1080I or 720P
Internal PLL requires no external loop filter
Selectable rising or falling clock edge for data
alignment
Compatible with Spread Spectrum clock source
Reduced LVDS output voltage swing mode
(selectable) to minimize EMI
CMOS/TTL data inputs can be configured for
reduced input voltage swing
Single 3.3 V supply
Low power consumption CMOS design
Power down mode
64-pin TQFP lead free package
Block Diagram
TA+
Parallel
to Serial
TA0-6
TA-
TB+
TB-
TC+
TC-
TD+
TD-
TE+
TE-
PLL
TB0-6
TC0-6
TE0-6
CLKIN
(8 to 135 MHz)
/PWDN
TD0-6
RS
R/F
7
7
7
7
7
TCLK+
TCLK-
T
RIPLE
10-B
IT
LVDS T
RANSMITTER
FOR
V
IDEO
V103
V103 Datasheet
2
11/23/06
Revision 2.0
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst. com
Pin Assignment
12
1
11
2
10
TD5
3
9
GND
4
5
6
7
8
16
15
14
13
64-pin TQFP
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
TD6
TE0
TE2
VCC
TE3
TE1
TE4
GND
TE5
CLKIN
/PWDN
PLLGND
PLLVCC
TE6
TA0
TA2
TA1
TA3
RS
TB2
TA4
TA5
GND
TA6
TB0
TB1
TB3
TB4
GND
TB5
17
18
19
20
21
22
23
24
25
26
27
28
L
VDSG
ND
TE+
TE
-
TD
+
TD
-
TC
L
K
+
TC
L
K
-
TC
+
TC
-
L
V
D
SVCC
TB+
L
VDSG
ND
32
31
30
29
L
VDSG
ND
TA
-
TB
-
TA
+
49
50
51
52
53
54
55
56
TB
6
TC
0
VC
C
TC
1
TC
2
TC
3
TC
4
GN
D
57
58
59
60
61
62
63
64
TC
5
TC
6
TD
0
R/
F
TD
1
TD
2
TD
3
TD
4
T
RIPLE
10-B
IT
LVDS T
RANSMITTER
FOR
V
IDEO
V103
V103 Datasheet
3
11/23/06
Revision 2.0
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst. com
Pin Descriptions
RS Input Voltage Configuration to set LVDS Output Swing and Data Input Swing
Note 1: Refer to DC Electrical Characteristics.
Pin
Number
Pin
Name
Pin Type
Pin Description
30, 31
TA+, TA-
LVDS OUT
LVDS Serial Data Output Pairs
28, 29
TB+, TB-
24, 25
TC+, TC-
20, 21
TD+, TD-
18, 19
TE+, TE-
22, 23
TCLK+, TCLK-
LVDS OUT
LVDS Reference Clock Output Pair
33, 34, 35, 36,
37, 38, 40
TA0 ~ TA6
IN
CMOS/TTL (or small signal) Data Bit Inputs
41, 42, 44, 45,
46, 48, 49
TB0 ~ TB6
50, 52, 53, 54,
55, 57, 58
TC0 ~ TC6
59, 61, 62, 63,
64, 1, 3
TD0 ~ TD6
4, 5, 6, 8, 9, 11,
16
TE0 ~ TE6
13
/PWDN
IN
High: Normal device operation
Low: Power down; all outputs become high impedance
43
RS
IN
Voltage level on this pin sets LVDS output swing voltage and data input
swing voltage; refer to the table at the bottom of this page.
60
R/F
IN
Input Clock triggering edge select. High: Rising edge; Low: Falling edge.
51, 7
VCC
Power
Power supply pins for TTL inputs and digital circuitry.
12
CLKIN
IN
Clock Input.
2, 10, 39, 47,
56
GND
Ground
Ground pins for TTL inputs and digital circuitry.
27
LVDSVCC
Power
Power supply pins for LVDS outputs.
17, 26, 32
LVDSGND
Ground
Ground pins for LVDS outputs.
15
PLLVCC
Power
Power supply pin for PLL circuitry.
14
PLLGND
Ground
Ground pin for PLL circuitry.
RS Input Voltage
LVDS Output Swing
CMOS/TTL Input Configuration (Input Voltage Swing)
VCC
350 mV
Standard Configuration
1
0.6 ~ 1.4 V (VREF
1
)
350 mV
Small Input Swing Configuration
1
GND
200 mV
Standard Configuration
1
T
RIPLE
10-B
IT
LVDS T
RANSMITTER
FOR
V
IDEO
V103
V103 Datasheet
4
11/23/06
Revision 2.0
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst. com
External Components
Decoupling capacitors should be used for all power pins. The V103 requires no other external components.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the V103. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
Item
Rating
Supply Voltage, VCC
-0.3 V to +4.0 V
CMOS/TTL Input Voltage
-0.3 V to VCC+0.3 V
CMOS/TTL Output Voltage
-0.3 V to VCC+0.3 V
LVDS Driver Output Voltage
-0.3 V to VCC+0.3 V
Storage Temperature
-55 to +150
C
Junction Temperature
120
C
Soldering Temperature (10 seconds)
260
C
Maximum Power Dissipation @ 25C
1.0 W
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
0
+70
C
Power Supply Voltage (measured in respect to GND)
+3.0
+3.3
+3.6
V
T
RIPLE
10-B
IT
LVDS T
RANSMITTER
FOR
V
IDEO
V103
V103 Datasheet
5
11/23/06
Revision 2.0
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst. com
DC Electrical Characteristics
VDD=3.3 V 10%,
Ambient temperature 0 to +70
C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
CMOS/TTL Inputs, Standard Configuration
Input High Voltage
V
IH
RS=VCC or GND
2.00
VCC
V
Input Low Voltage
V
IL
RS=VCC or GND
GND
0.80
V
Input Current
I
INC
0V<VIN<VCC
10
A
CMOS/TTL Inputs, Small Input Swing Configuration
Max Input Swing Voltage
V
DDQ
1
V
REF
= V
RS
= V
DDQ
/2
1.2
2.8
V
Input Reference Voltage into pin RS
V
REF
V
DDQ
/2
V
High Level Input Voltage
(for small input swing condition)
V
SH
2
V
REF
=V
DDQ
/2
V
DDQ
/2
+0.1V
V
Low Level Input Voltage
(for small input swing condition)
V
SL
2
V
REF
=V
DDQ
/2
V
DDQ
/2
-0.1V
V
Note 1: V
DDQ
voltage defines the max voltage of the small swing input and is not an actual input into the device.
Note 2: Small input swing voltage is applied to TA[6:0], TB[6:0], TC[6:0], TD[6:0], TE[6:0], and CLKIN.
LVDS Transmitter DC Specifications
Differential Output Voltage,
R
L
= 100
V
OD
Normal swing
RS = VCC
250
350
450
mV
Reduced swing
RS = GND
100
200
300
mV
Change in V
OD
Between Complimentary
Output States
DV
OD
RL = 100
35
mV
Common Mode Voltage
V
OC
1.125
1.250
1.375
V
Change in V
OC
Between Complimentary
Output States
DV
OC
35
mV
Output Short Circuit Current
I
OS
V
OUT
= 0V, RL = 100
-24
mA
Output Tri-State Current
I
OZ
/PWDN = 0V,
V
OUT
= 0V to VCC
10
A
Supply Current
Transmitter Supply Current
I
TCCG
R
L
= 100
, C
L
=5 pF,
VCC = 3.3 V, RS = VCC
Gray Scale Pattern
f = 85 MHz
58
64
mA
f =135 MHz
70
76
mA
R
L
= 100
, C
L
=5 pF,
VCC = 3.3 V, RS = GND
Gray Scale Pattern
f = 85 MHz
44
50
mA
f =135 MHz
56
62
mA
Transmitter Supply Current
I
TCCW
R
L
= 100
, C
L
= 5 pF,
VCC = 3.3 V, RS = VCC
Worst Case Pattern
f = 85 MHz
69
75
mA
f =135 MHz
87
93
mA
R
L
= 100
, C
L
= 5 pF,
VCC = 3.3 V, RS = GND
Worst Case Pattern
f = 85 MHz
55
61
mA
f =135 MHz
73
79
mA
Transmitter Power Down Supply Current
I
TCCS
/PWDN = L
10
A
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