HTML datasheet архив (поиск документации на электронные компоненты) Поиск даташита (1.687.043 компонентов)
Где искать

Datasheet: 026BI01L (Integrated Circuit Systems)

LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER

 

Скачать: PDF   ZIP
Integrated Circuit Systems

Document Outline

83026BMI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
1
Integrated
Circuit
Systems, Inc.
ICS83026I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS830 26I-01 is a low skew, 1-to-2 Dif-
ferential-to-LVCMOS/LVTTL Fanout Buffer and
a member of the HiPerClock S TM
family of
H i g h Pe r fo r m a n c e C l o ck S o l u t i o n s f r o m
ICS. The differential input can accept most dif-
ferential signal types (LVPECL, LVDS, LVHSTL, HCSL and
SSTL) and translate to two single-ended LVCMOS/LVTTL out-
puts. The small 8-lead SOIC footprint makes this device ideal
for use in applications with limited board space.
F
EATURES
Two LVCMOS / LVTTL outputs
Differential CLK, nCLK input pair
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Maximum output frequency: 350MHz
Output skew: 15ps (maximum)
Part-to-part skew: 600ps (maximum)
Additive phase jitter, RMS: 0.03ps (typical)
Small 8 lead SOIC package saves board space
3.3V core, 3.3V, 2.5V or 1.8V output operating supply
-40C to 85C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS83026I-01
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View
V
DD
CLK
nCLK
OE
1
2
3
4
Q0
Q1
CLK
nCLK
OE
HiPerClockSTM
ICS
V
DDO
Q0
Q1
GND
8
7
6
5
ICS83026I-01
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
V
DD
CLK
nCLK
OE
1
2
3
4
V
DDO
Q0
Q1
GND
8
7
6
5
83026BMI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
2
Integrated
Circuit
Systems, Inc.
ICS83026I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
r
e
b
m
u
N
e
m
a
N
e
p
y
T
n
o
i
t
p
i
r
c
s
e
D
1
V
D
D
r
e
w
o
P
.
n
i
p
y
l
p
p
u
s
e
v
i
t
i
s
o
P
2
K
L
C
t
u
p
n
I
n
w
o
d
ll
u
P
.
t
u
p
n
i
k
c
o
l
c
l
a
i
t
n
e
r
e
f
f
i
d
g
n
i
t
r
e
v
n
i
-
n
o
N
3
K
L
C
n
t
u
p
n
I
/
p
u
ll
u
P
n
w
o
d
ll
u
P
V
.
t
u
p
n
i
k
c
o
l
c
l
a
i
t
n
e
r
e
f
f
i
d
g
n
i
t
r
e
v
n
I
D
D
.
g
n
i
t
a
o
l
f
t
f
e
l
n
e
h
w
t
l
u
a
f
e
d
2
/
4
E
O
t
u
p
n
I
p
u
ll
u
P
n
i
e
r
a
s
t
u
p
t
u
o
,
W
O
L
n
e
h
W
.
d
e
l
b
a
n
e
e
r
a
s
t
u
p
t
u
o
,
H
G
I
H
n
e
h
W
.
e
l
b
a
n
e
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
e
t
a
t
S
e
c
n
a
d
e
p
m
I
h
g
i
H
5
D
N
G
r
e
w
o
P
.
d
n
u
o
r
g
y
l
p
p
u
s
r
e
w
o
P
6
1
Q
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
t
u
p
t
u
o
k
c
o
l
C
7
0
Q
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
t
u
p
t
u
o
k
c
o
l
C
8
V
O
D
D
r
e
w
o
P
.
n
i
p
y
l
p
p
u
s
t
u
p
t
u
O
:
E
T
O
N
p
u
ll
u
P
d
n
a
n
w
o
d
ll
u
P
.
s
e
u
l
a
v
l
a
c
i
p
y
t
r
o
f
,
s
c
i
t
s
i
r
e
t
c
a
r
a
h
C
n
i
P
,
2
e
l
b
a
T
e
e
S
.
s
r
o
t
s
i
s
e
r
t
u
p
n
i
l
a
n
r
e
t
n
i
o
t
r
e
f
e
r
t
u
p
n
I
s
t
u
p
t
u
O
E
O
1
Q
,
0
Q
0
Z
i
H
1
e
v
i
t
c
A
T
ABLE
3. C
ONTROL
F
UNCTION
T
ABLE
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
C
N
I
e
c
n
a
t
i
c
a
p
a
C
t
u
p
n
I
4
F
p
C
D
P
e
c
n
a
t
i
c
a
p
a
C
n
o
i
t
a
p
i
s
s
i
D
r
e
w
o
P
)
t
u
p
t
u
o
r
e
p
(
V
D
D
V
,
O
D
D
V
5
6
4
.
3
=
7
1
F
p
V
D
D
V
,
V
5
6
4
.
3
=
O
D
D
V
5
2
6
.
2
=
6
1
F
p
V
D
D
V
,
V
5
6
4
.
3
=
O
D
D
V
5
9
.
1
=
5
1
F
p
R
P
U
L
L
U
P
r
o
t
s
i
s
e
R
p
u
ll
u
P
t
u
p
n
I
1
5
k
R
N
W
O
D
L
L
U
P
r
o
t
s
i
s
e
R
n
w
o
d
ll
u
P
t
u
p
n
I
1
5
k
R
T
U
O
e
c
n
a
d
e
p
m
I
t
u
p
t
u
O
V
D
D
V
,
O
D
D
V
3
.
3
=
7
V
D
D
V
,
V
3
.
3
=
O
D
D
V
5
.
2
=
8
V
D
D
V
,
V
3
.
3
=
O
D
D
V
8
.
1
=
0
1
83026BMI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
3
Integrated
Circuit
Systems, Inc.
ICS83026I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V 5%, V
DDO
= 1.71V
TO
3.465V, T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
e
v
i
t
i
s
o
P
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
O
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
t
u
p
t
u
O
5
3
1
.
3
3
.
3
5
6
4
.
3
V
5
7
3
.
2
5
.
2
5
2
6
.
2
V
1
7
.
1
8
.
1
9
8
.
1
V
I
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
0
1
A
m
I
O
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
t
u
p
t
u
O
3
A
m
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V 5%, V
DDO
= 2.375V
TO
3.465V, T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
H
I
e
g
a
t
l
o
V
h
g
i
H
t
u
p
n
I
E
O
2
V
D
D
3
.
0
+
V
V
L
I
e
g
a
t
l
o
V
w
o
L
t
u
p
n
I
E
O
3
.
0
-
8
.
0
V
I
H
I
t
n
e
r
r
u
C
h
g
i
H
t
u
p
n
I
E
O
V
D
D
V
=
N
I
V
5
6
4
.
3
=
5
A
I
L
I
t
n
e
r
r
u
C
w
o
L
t
u
p
n
I
E
O
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
0
5
1
-
A
V
H
O
;
e
g
a
t
l
o
V
h
g
i
H
t
u
p
t
u
O
1
E
T
O
N
V
O
D
D
V
5
3
1
.
3
=
6
.
2
V
V
O
D
D
V
5
7
3
.
2
=
8
.
1
V
V
L
O
;
e
g
a
t
l
o
V
w
o
L
t
u
p
t
u
O
1
E
T
O
N
5
.
0
V
0
5
h
t
i
w
d
e
t
a
n
i
m
r
e
t
s
t
u
p
t
u
O
:
1
E
T
O
N
V
o
t
O
D
D
,
n
o
i
t
c
e
s
n
o
i
t
a
m
r
o
f
n
I
t
n
e
m
e
r
u
s
a
e
M
r
e
t
e
m
a
r
a
P
e
e
S
.
2
/
.
s
m
a
r
g
a
i
d
"
t
i
u
c
r
i
C
t
s
e
T
d
a
o
L
t
u
p
t
u
O
"
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
8 Lead SOIC
112.7C/W (0 lfpm)
8 Lead TSSOP
101.7C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V 5%, V
DDO
= 1.8V 5%, T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
H
I
e
g
a
t
l
o
V
h
g
i
H
t
u
p
n
I
E
O
2
V
D
D
3
.
0
+
V
V
L
I
e
g
a
t
l
o
V
w
o
L
t
u
p
n
I
E
O
3
.
0
-
8
.
0
V
I
H
I
t
n
e
r
r
u
C
h
g
i
H
t
u
p
n
I
E
O
V
D
D
V
=
N
I
V
5
6
4
.
3
=
5
A
I
L
I
t
n
e
r
r
u
C
w
o
L
t
u
p
n
I
E
O
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
0
5
1
-
A
V
H
O
e
g
a
t
l
o
V
h
g
i
H
t
u
p
t
u
O
I
H
O
A
0
0
1
-
=
V
O
D
D
2
.
0
-
V
I
H
O
A
m
2
-
=
V
O
D
D
5
4
.
0
-
V
V
L
O
e
g
a
t
l
o
V
w
o
L
t
u
p
t
u
O
I
L
O
A
0
0
1
=
2
.
0
V
I
L
O
A
m
2
=
5
4
.
0
V
83026BMI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
4
Integrated
Circuit
Systems, Inc.
ICS83026I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
4A. AC C
HARACTERISTICS
,
V
DD
= 3.3V 5%, V
DDO
= 3.3V 5%, T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
X
A
M
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
0
5
3
z
H
M
t
D
P
1
E
T
O
N
;
y
a
l
e
D
n
o
i
t
a
g
a
p
o
r
P
z
H
M
0
5
3
3
.
1
9
.
1
5
.
2
s
n
t
)
o
(
k
s
4
,
2
E
T
O
N
;
w
e
k
S
t
u
p
t
u
O
5
1
s
p
t
)
p
p
(
k
s
4
,
3
E
T
O
N
;
w
e
k
S
t
r
a
P
-
o
t
-
t
r
a
P
0
0
9
s
p
t
t
i
j
o
t
r
e
f
e
r
,
S
M
R
,
r
e
t
t
i
J
e
s
a
h
P
e
v
i
t
i
d
d
A
r
e
f
f
u
B
n
o
i
t
c
e
S
r
e
t
t
i
J
e
s
a
h
P
e
v
i
t
i
d
d
A
3
0
.
0
s
p
t
R
t
/
F
e
m
i
T
ll
a
F
/
e
s
i
R
t
u
p
t
u
O
%
0
8
o
t
%
0
2
0
5
1
0
0
8
s
p
c
d
o
e
l
c
y
C
y
t
u
D
t
u
p
t
u
O
z
H
M
6
6
8
4
2
5
%
z
H
M
7
6
z
H
M
6
6
1
5
4
5
5
%
z
H
M
7
6
1
z
H
M
0
5
3
0
4
0
6
%
V
o
t
t
n
i
o
p
g
n
i
s
s
o
r
c
t
u
p
n
i
l
a
i
t
n
e
r
e
f
f
i
d
e
h
t
m
o
r
f
d
e
r
u
s
a
e
M
:
1
E
T
O
N
O
D
D
.
t
u
p
t
u
o
e
h
t
f
o
2
/
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
h
t
i
w
d
n
a
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
t
a
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
2
E
T
O
N
V
t
a
d
e
r
u
s
a
e
M
O
D
D
.
2
/
h
t
i
w
d
n
a
s
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
t
a
g
n
i
t
a
r
e
p
o
s
e
c
i
v
e
d
t
n
e
r
e
f
f
i
d
n
o
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
3
E
T
O
N
V
t
a
d
e
r
u
s
a
e
m
e
r
a
s
t
u
p
t
u
o
e
h
t
,
e
c
i
v
e
d
h
c
a
e
n
o
s
t
u
p
n
i
f
o
e
p
y
t
e
m
a
s
e
h
t
g
n
i
s
U
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
O
D
D
.
2
/
.
6
d
r
a
d
n
a
t
S
C
E
D
E
J
h
t
i
w
e
c
n
a
d
r
o
c
c
a
n
i
d
e
n
i
f
e
d
s
i
r
e
t
e
m
a
r
a
p
s
i
h
T
:
4
E
T
O
N
T
ABLE
3D. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V 5%, V
DDO
= 1.71V
TO
3.465V, T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
I
H
I
t
n
e
r
r
u
C
h
g
i
H
t
u
p
n
I
K
L
C
n
V
N
I
V
=
D
D
V
5
6
4
.
3
=
0
5
1
A
K
L
C
V
N
I
V
=
D
D
V
5
6
4
.
3
=
0
5
1
A
I
L
I
t
n
e
r
r
u
C
w
o
L
t
u
p
n
I
K
L
C
n
V
N
I
V
,
V
0
=
D
D
V
5
6
4
.
3
=
0
5
1
-
A
K
L
C
V
N
I
V
,
V
0
=
D
D
V
5
6
4
.
3
=
5
-
A
V
P
P
1
E
T
O
N
;
e
g
a
t
l
o
V
t
u
p
n
I
k
a
e
P
-
o
t
-
k
a
e
P
5
1
.
0
3
.
1
V
V
R
M
C
3
,
2
E
T
O
N
;
e
g
a
t
l
o
V
t
u
p
n
I
e
d
o
M
n
o
m
m
o
C
5
.
0
+
D
N
G
V
D
D
5
8
.
0
-
V
V
:
1
E
T
O
N
P
P
V
p
e
e
k
o
t
l
e
v
e
l
t
e
s
f
f
o
t
n
e
i
c
i
f
f
u
s
s
i
e
r
e
h
t
t
a
h
t
d
e
d
i
v
o
r
p
V
3
.
1
d
e
e
c
x
e
n
a
c
L
I
.
V
0
>
s
n
o
i
t
a
c
il
p
p
a
d
e
d
n
e
e
l
g
n
i
s
r
o
F
:
2
E
T
O
N
,
V
s
i
K
L
C
n
,
K
L
C
r
o
f
e
g
a
t
l
o
v
t
u
p
n
i
m
u
m
i
x
a
m
e
h
t
D
D
.
V
3
.
0
+
s
i
e
g
a
t
l
o
v
e
d
o
m
n
o
m
m
o
C
:
3
E
T
O
N
V
s
a
d
e
n
i
f
e
d
H
I
.
83026BMI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
5
Integrated
Circuit
Systems, Inc.
ICS83026I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
4B. AC C
HARACTERISTICS
,
V
DD
= 3.3V 5%, V
DDO
= 2.5V 5%, T
A
= -40C
TO
85C
T
ABLE
4C. AC C
HARACTERISTICS
,
V
DD
= 3.3V 5%, V
DDO
= 1.8V 5%, T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
X
A
M
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
0
5
3
z
H
M
t
D
P
1
E
T
O
N
;
y
a
l
e
D
n
o
i
t
a
g
a
p
o
r
P
z
H
M
0
5
3
5
.
1
0
.
2
6
.
2
s
n
t
)
o
(
k
s
4
,
2
E
T
O
N
;
w
e
k
S
t
u
p
t
u
O
5
1
s
p
t
)
p
p
(
k
s
4
,
3
E
T
O
N
;
w
e
k
S
t
r
a
P
-
o
t
-
t
r
a
P
0
5
7
s
p
t
t
i
j
,
r
e
t
t
i
J
e
s
a
h
P
e
v
i
t
i
d
d
A
r
e
f
f
u
B
e
s
a
h
P
e
v
i
t
i
d
d
A
o
t
r
e
f
e
r
,
S
M
R
n
o
i
t
c
e
S
r
e
t
t
i
J
3
0
.
0
s
p
t
R
t
/
F
e
m
i
T
ll
a
F
/
e
s
i
R
t
u
p
t
u
O
%
0
8
o
t
%
0
2
0
5
1
0
0
8
s
p
c
d
o
e
l
c
y
C
y
t
u
D
t
u
p
t
u
O
z
H
M
6
6
8
4
2
5
%
z
H
M
7
6
z
H
M
6
6
1
6
4
4
5
%
z
H
M
7
6
1
z
H
M
0
5
3
0
4
0
6
%
V
o
t
t
n
i
o
p
g
n
i
s
s
o
r
c
t
u
p
n
i
l
a
i
t
n
e
r
e
f
f
i
d
e
h
t
m
o
r
f
d
e
r
u
s
a
e
M
:
1
E
T
O
N
O
D
D
.
t
u
p
t
u
o
e
h
t
f
o
2
/
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
h
t
i
w
d
n
a
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
t
a
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
2
E
T
O
N
V
t
a
d
e
r
u
s
a
e
M
O
D
D
.
2
/
h
t
i
w
d
n
a
s
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
t
a
g
n
i
t
a
r
e
p
o
s
e
c
i
v
e
d
t
n
e
r
e
f
f
i
d
n
o
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
3
E
T
O
N
V
t
a
d
e
r
u
s
a
e
m
e
r
a
s
t
u
p
t
u
o
e
h
t
,
e
c
i
v
e
d
h
c
a
e
n
o
s
t
u
p
n
i
f
o
e
p
y
t
e
m
a
s
e
h
t
g
n
i
s
U
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
O
D
D
.
2
/
.
5
6
d
r
a
d
n
a
t
S
C
E
D
E
J
h
t
i
w
e
c
n
a
d
r
o
c
c
a
n
i
d
e
n
i
f
e
d
s
i
r
e
t
e
m
a
r
a
p
s
i
h
T
:
4
E
T
O
N
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
X
A
M
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
0
5
3
z
H
M
t
D
P
1
E
T
O
N
;
y
a
l
e
D
n
o
i
t
a
g
a
p
o
r
P
z
H
M
0
5
3
9
.
1
5
.
2
1
.
3
s
n
t
)
o
(
k
s
4
,
2
E
T
O
N
;
w
e
k
S
t
u
p
t
u
O
5
1
s
p
t
)
p
p
(
k
s
4
,
3
E
T
O
N
;
w
e
k
S
t
r
a
P
-
o
t
-
t
r
a
P
0
0
6
s
p
t
t
i
j
,
r
e
t
t
i
J
e
s
a
h
P
e
v
i
t
i
d
d
A
r
e
f
f
u
B
e
s
a
h
P
e
v
i
t
i
d
d
A
o
t
r
e
f
e
r
,
S
M
R
n
o
i
t
c
e
S
r
e
t
t
i
J
3
0
.
0
s
p
t
R
t
/
F
e
m
i
T
ll
a
F
/
e
s
i
R
t
u
p
t
u
O
%
0
8
o
t
%
0
2
0
0
2
0
0
9
s
p
c
d
o
e
l
c
y
C
y
t
u
D
t
u
p
t
u
O
z
H
M
6
6
8
4
2
5
%
z
H
M
7
6
z
H
M
6
6
1
3
4
7
5
%
z
H
M
7
6
1
z
H
M
0
5
3
0
4
0
6
%
V
o
t
t
n
i
o
p
g
n
i
s
s
o
r
c
t
u
p
n
i
l
a
i
t
n
e
r
e
f
f
i
d
e
h
t
m
o
r
f
d
e
r
u
s
a
e
M
:
1
E
T
O
N
O
D
D
.
t
u
p
t
u
o
e
h
t
f
o
2
/
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
h
t
i
w
d
n
a
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
t
a
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
2
E
T
O
N
V
t
a
d
e
r
u
s
a
e
M
O
D
D
.
2
/
h
t
i
w
d
n
a
s
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
t
a
g
n
i
t
a
r
e
p
o
s
e
c
i
v
e
d
t
n
e
r
e
f
f
i
d
n
o
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
3
E
T
O
N
V
t
a
d
e
r
u
s
a
e
m
e
r
a
s
t
u
p
t
u
o
e
h
t
,
e
c
i
v
e
d
h
c
a
e
n
o
s
t
u
p
n
i
f
o
e
p
y
t
e
m
a
s
e
h
t
g
n
i
s
U
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
O
D
D
.
2
/
.
5
6
d
r
a
d
n
a
t
S
C
E
D
E
J
h
t
i
w
e
c
n
a
d
r
o
c
c
a
n
i
d
e
n
i
f
e
d
s
i
r
e
t
e
m
a
r
a
p
s
i
h
T
:
4
E
T
O
N
83026BMI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
6
Integrated
Circuit
Systems, Inc.
ICS83026I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
A
DDITIVE
P
HASE
J
ITTER
Input/Output Additive
Phase Jitter
at 155.52MHz
= 0.03ps typical
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
SSB P
HASE
N
OISE
dBc/H
Z
83026BMI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
7
Integrated
Circuit
Systems, Inc.
ICS83026I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
SCOPE
Qx
LVCMOS
3.3VC
ORE
/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.40.125V
V
DDO
-0.9V0.45V
V
DD
0.9V0.45V
SCOPE
Qx
LVCMOS
3.3VC
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.05V0.103V
V
DDO
-1.25V5%
V
DD
1.25V5%
3.3VC
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V5%
-1.65V5%
D
IFFERENTIAL
I
NPUT
L
EVEL
O
UTPUT
S
KEW
P
ART
-
TO
-P
ART
S
KEW
V
CMR
Cross Points
V
PP
GND
CLK
nCLK
V
DD
t
sk(o)
V
DDO
2
V
DDO
2
Qy
Qx
t
sk(pp)
V
DDO
2
V
DDO
2
Qy
Qx
PART 1
PART 2
V
DD,
V
DDO
GND
GND
GND
83026BMI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
8
Integrated
Circuit
Systems, Inc.
ICS83026I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
P
ROPAGATION
D
ELAY
Q0, Q1
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
t
PD
V
DDO
2
CLK
nCLK
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
x 100%
t
PW
Q0, Q1
83026BMI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
9
Integrated
Circuit
Systems, Inc.
ICS83026I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
Figure 1
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
O
UTPUTS
:
LVCMOS O
UTPUT
:
All unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
R
ECOMMENDATIONS
FOR
U
NUSED
O
UTPUT
P
INS
83026BMI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
10
Integrated
Circuit
Systems, Inc.
ICS83026I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
F
IGURE
2C. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
2B. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
2D. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 2A to 2E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
2A.
H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 2A,
the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
F
IGURE
2E.
H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
83026BMI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
11
Integrated
Circuit
Systems, Inc.
ICS83026I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
S
CHEMATIC
E
XAMPLE
Figure 3
shows an application schematic example of ICS83026I-
01. The ICS83026I-01 CLK/nCLK input can directly accepts
various types of differential signal. In this example, the input is
driven by an LVDS driver. The ICS83026I-01 outputs are
VDDO
R1
43
LVDS
VDD
R4
100
VDD=3.3V
LVCMOS
Zo = 50 Ohm
R3
1K
C2
0.1u
3.3V
Zo = 50 Ohm
VDDO= 3.3V, 2.5V or 1.8V
Zo = 50 Ohm
U1
ICS83026I-01
1
2
3
4
8
7
6
5
VDD
CLK
nCLK
OE
VDDO
Q0
Q1
GND
LVCMOS
R2
43
C1
0.1u
VDD
Zo = 50 Ohm
F
IGURE
3. ICS83026I-01 S
CHEMATIC
E
XAMPLE
LVCMOS drivers. In this example, series termination approach
is shown. Additional termination approaches are shown in the
LVCMOS Termination Application Note.
T
RANSISTOR
C
OUNT
The transistor count for ICS83026I-0I is: 260
T
ABLE
5A.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
SOIC


JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
153.3C/W
128.5C/W
115.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7C/W
103.3C/W
97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
R
ELIABILITY
I
NFORMATION
T
ABLE
5B.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
TSSOP


JA
by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
90.5C/W
89.8C/W
83026BMI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
12
Integrated
Circuit
Systems, Inc.
ICS83026I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
6A. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-012
P
ACKAGE
O
UTLINE
- S
UFFIX
M
FOR
8 L
EAD
SOIC
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
M
U
M
I
N
I
M
M
U
M
I
X
A
M
N
8
A
5
3
.
1
5
7
.
1
1
A
0
1
.
0
5
2
.
0
B
3
3
.
0
1
5
.
0
C
9
1
.
0
5
2
.
0
D
0
8
.
4
0
0
.
5
E
0
8
.
3
0
0
.
4
e
C
I
S
A
B
7
2
.
1
H
0
8
.
5
0
2
.
6
h
5
2
.
0
0
5
.
0
L
0
4
.
0
7
2
.
1
0
8
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
8 L
EAD
TSSOP
T
ABLE
6B. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
m
u
m
i
n
i
M
m
u
m
i
x
a
M
N
8
A
-
-
0
2
.
1
1
A
5
0
.
0
5
1
.
0
2
A
0
8
.
0
5
0
.
1
b
9
1
.
0
0
3
.
0
c
9
0
.
0
0
2
.
0
D
0
9
.
2
0
1
.
3
E
C
I
S
A
B
0
4
.
6
1
E
0
3
.
4
0
5
.
4
e
C
I
S
A
B
5
6
.
0
L
5
4
.
0
5
7
.
0
0
8
a
a
a
-
-
0
1
.
0
83026BMI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
13
Integrated
Circuit
Systems, Inc.
ICS83026I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
7. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
r
e
b
m
u
N
r
e
d
r
O
/
t
r
a
P
g
n
i
k
r
a
M
e
g
a
k
c
a
P
g
n
i
g
a
k
c
a
P
g
n
i
p
p
i
h
S
e
r
u
t
a
r
e
p
m
e
T
1
0
-
I
M
B
6
2
0
3
8
S
C
I
1
0
I
B
6
2
0
3
C
I
O
S
d
a
e
l
8
e
b
u
t
C
5
8
o
t
C
0
4
-
T
1
0
-
I
M
B
6
2
0
3
8
S
C
I
1
0
I
B
6
2
0
3
C
I
O
S
d
a
e
l
8
l
e
e
r
&
e
p
a
t
0
0
5
2
C
5
8
o
t
C
0
4
-
F
L
1
0
-
I
M
B
6
2
0
3
8
S
C
I
L
1
0
I
B
6
2
0
C
I
O
S
"
e
e
r
F
-
d
a
e
L
"
d
a
e
l
8
e
b
u
t
C
5
8
o
t
C
0
4
-
T
F
L
1
0
-
I
M
B
6
2
0
3
8
S
C
I
L
1
0
I
B
6
2
0
C
I
O
S
"
e
e
r
F
-
d
a
e
L
"
d
a
e
l
8
l
e
e
r
&
e
p
a
t
0
0
5
2
C
5
8
o
t
C
0
4
-
1
0
-
I
G
B
6
2
0
3
8
S
C
I
1
0
B
6
2
P
O
S
S
T
d
a
e
l
8
e
b
u
t
C
5
8
o
t
C
0
4
-
T
1
0
-
I
G
B
6
2
0
3
8
S
C
I
1
0
B
6
2
P
O
S
S
T
d
a
e
l
8
l
e
e
r
&
e
p
a
t
0
0
5
2
C
5
8
o
t
C
0
4
-
F
L
1
0
-
I
G
B
6
2
0
3
8
S
C
I
D
B
T
P
O
S
S
T
"
e
e
r
F
-
d
a
e
L
"
d
a
e
l
8
e
b
u
t
C
5
8
o
t
C
0
4
-
T
F
L
1
0
-
I
G
B
6
2
0
3
8
S
C
I
D
B
T
P
O
S
S
T
"
e
e
r
F
-
d
a
e
L
"
d
a
e
l
8
l
e
e
r
&
e
p
a
t
0
0
5
2
C
5
8
o
t
C
0
4
-
.
t
n
a
il
p
m
o
c
S
H
o
R
e
r
a
d
n
a
n
o
i
t
a
r
u
g
i
f
n
o
c
e
e
r
F
-
b
P
e
h
t
e
r
a
r
e
b
m
u
n
t
r
a
p
e
h
t
o
t
x
i
f
f
u
s
"
F
L
"
n
a
h
t
i
w
d
e
r
e
d
r
o
e
r
a
t
a
h
t
s
t
r
a
P
:
E
T
O
N
83026BMI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
14
Integrated
Circuit
Systems, Inc.
ICS83026I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
E
E
H
S
Y
R
O
T
S
I
H
N
O
I
S
I
V
E
R
v
e
R
e
l
b
a
T
e
g
a
P
e
g
n
a
h
C
f
o
n
o
i
t
p
i
r
c
s
e
D
e
t
a
D
A
7
T
1
3
1
1
2
1
3
1
.
t
n
e
m
n
g
i
s
s
A
n
i
P
o
t
e
g
a
k
c
a
p
P
O
S
S
T
d
a
e
L
8
d
e
d
d
A
l
a
m
r
e
h
T
e
g
a
k
c
a
P
o
t
P
O
S
S
T
d
a
e
L
8
d
e
d
d
a
-
s
g
n
i
t
a
R
m
u
m
i
x
a
M
e
t
u
l
o
s
b
A
.
e
c
n
a
d
e
p
m
I
.
e
l
b
a
t
n
o
i
t
a
m
r
o
f
n
I
y
t
il
i
b
a
il
e
R
P
O
S
S
T
d
a
e
L
8
d
e
d
d
A
.
s
n
o
i
s
n
e
m
i
D
e
g
a
k
c
a
P
d
n
a
e
n
il
t
u
O
e
g
a
k
c
a
P
P
O
S
S
T
d
a
e
L
8
d
e
d
d
A
.
n
o
i
t
a
m
r
o
f
n
i
g
n
i
r
e
d
r
o
P
O
S
S
T
d
a
e
L
8
d
e
d
d
a
-
e
l
b
a
T
n
o
i
t
a
m
r
o
f
n
I
g
n
i
r
e
d
r
O
4
0
/
5
2
/
6
A
6
.
t
o
l
p
n
o
s
i
x
a
X
d
e
t
c
e
r
r
o
c
-
r
e
t
t
i
J
e
s
a
h
P
e
v
i
t
i
d
d
A
5
0
/
2
/
8
A
C
3
T
3
.
L
I
I
d
n
a
H
I
I
r
o
f
s
n
o
i
t
i
d
n
o
C
t
s
e
T
d
e
t
c
e
r
r
o
c
-
s
c
i
t
s
i
r
e
t
c
a
r
a
h
C
C
D
S
O
M
C
V
L
5
0
/
2
1
/
8
A
7
T
1
9
3
1
t
e
ll
u
b
e
e
r
f
-
d
a
e
l
d
e
d
d
a
-
n
o
i
t
c
e
S
s
e
r
u
t
a
e
F
d
e
d
d
A
.
s
n
i
P
t
u
p
t
u
O
d
e
s
u
n
U
r
o
f
s
n
o
i
t
a
d
n
e
m
m
o
c
e
R
.
e
t
o
n
d
n
a
,
g
n
i
k
r
a
m
,
r
e
b
m
u
n
t
r
a
p
e
e
r
f
-
d
a
e
l
d
e
d
d
a
-
e
l
b
a
T
n
o
i
t
a
m
r
o
f
n
I
g
n
i
r
e
d
r
O
6
0
/
6
1
/
1
© 2017 • ChipFind
Контакты
Главная страница