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Datasheet: 01AL (Integrated Circuit Systems)

2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER

 

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Integrated Circuit Systems

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85301AK
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
1
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
G
ENERAL
D
ESCRIPTION
The ICS85301 is a high performance 2:1 Differ-
ential-to-LVPECL Multiplexer and a member of the
HiPerClockSTM family of High Performance Clock
Solutions from ICS. The ICS85301 can also per-
form differential translation because the differ-
ential inputs accept LVPECL, CML as well as LVDS levels.
The ICS85301 is packaged in a small 3mm x 3mm
16 VFQFN package, making it ideal for use on space con-
strained boards.
F
EATURES
2:1 LVPECL MUX
One LVPECL output
Two differential clock inputs can accept: LVPECL, LVDS,
CML
Maximum input/output frequency: 3GHz
Translates LVCMOS/LVTTL input signals to LVPECL levels
by using a resistor bias network on nPCLK0, nPCLK0
Propagation delay: 490ps (maximum)
Part-to-part skew: 150ps (maximum)
Additive phase jitter, RMS: 0.009ps (typical)
Full 3.3V or 2.5V operating supply
-40C to 85C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
HiPerClockSTM
ICS
ICS85301
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
Top View
PCLK0
nPCLK0
PCLK1
nPCLK1
V
EE
Q
nQ
V
EE
V
BB
CLK_SEL
nc
V
CC
nc
V
EE
V
EE
V
CC
1
2
3
4
12
11
10
9
5 6 7 8
16 15 14 13
0
1
PCLK0
nPCLK0
PCLK1
nPCLK1
CLK_SEL
V
BB
Q
nQ
PCLK0
nPCLK0
PCLK1
nPCLK1
V
BB
CLK_SEL
nc
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
nc
V
EE
V
EE
V
CC
V
EE
Q
nQ
V
EE
ICS85301
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
85301AK
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
2
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
1. P
IN
D
ESCRIPTIONS
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85301AK
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
3
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
T
ABLE
4C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V 5%
OR
2.5V 5%, T
A
= -40C
TO
85C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V 5%, T
A
= -40C
TO
85C
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A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5 V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
16 VFQFN
51.5C/W (0 lfpm)
16 TSSOP
89C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.5V 5%, T
A
= -40C
TO
85C
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,
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2
-
85301AK
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
4
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
T
ABLE
5A. AC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= -40C
TO
85C
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s
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V
2
-
85301AK
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
5
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
A
DDITIVE
P
HASE
J
ITTER
Additive Phase Jitter
3.3V or 2.5V @ 622MHz (12KHz to 20MHz)
= 0.009ps typical
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
SSB P
HASE
N
OISE
dBc/H
Z
85301AK
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
6
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
P
ART
-
TO
-P
ART
S
KEW
P
ROPAGATION
D
ELAY
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
V
CMR
Cross Points
V
PP
V
EE
nPCLK0,
nPCLK1
nPCLK0,
nPCLK1
V
CC
t
PD
Q
nQ
t
sk(pp)
PART 1
PART 2
Q0x
Qy
nQx
nQy
PCLK0,
PCLK1
nPCLK0,
nPCLK1
Q
nQ
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
SCOPE
Qx
nQx
LVPECL
2V
-1.3V 0.165V
V
CC
V
EE
SCOPE
Qx
nQx
LVPECL
2V
-0.5V 0.125V
V
CC
V
EE
85301AK
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
7
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
OD
O
UTPUT
R
ISE
/F
ALL
T
IME
I
NPUT
S
KEW
t
PD2
t
PD1
tsk(i) = |t
PD1
- t
PD2
|
tsk(i)
Q
nQ
PCLK0
nPCLK0
PCLK1
nPCLK1
85301AK
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
8
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
A
PPLICATION
I
NFORMATION
F
IGURE
1A. S
INGLE
E
NDED
LVCMOS S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
Figure 1A
shows an example of the differential input that
can be wired to accept single ended LVCMOS levels. The
reference voltage level V
BB
generated from the device is
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
LVCMOS L
EVELS
connected to the negative input. The C1 capacitor should
be located as close as possible to the input pin.
F
IGURE
1B. S
INGLE
E
NDED
LVPECL S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
Figure 1B
shows an example of the differential input that
can be wired to accept single ended LVPECL levels. The
reference voltage level V
BB
generated from the device is
connected to the negative input.
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
LVPECL L
EVELS
VCC
R2
1K
V_REF
C1
0.1u
R1
1K
Single Ended Clock Input
PCLK
nPCLK
VCC(or VDD)
CLK_IN
PCLK
nPCLK
VBB
85301AK
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
9
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
LVPECL C
LOCK
I
NPUT
I
NTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
SWING
and V
OH
must meet the V
PP
and V
CMR
input requirements.
Figures 2A to 2F
show inter-
face examples for the HiPerClockS PCLK/nPCLK input driven
by the most common driver types. The input interfaces sug-
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
F
IGURE
2A. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
AN
O
PEN
C
OLLECTOR
CML D
RIVER
F
IGURE
2B. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
B
UILT
-I
N
P
ULLUP
CML D
RIVER
F
IGURE
2C. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
F
IGURE
2F.
H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
3.3V LVDS D
RIVER
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
F
IGURE
2E. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
AN
SSTL D
RIVER
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
3.3V
HiPerClockS
PCLK
nPCLK
R2
84
R3
125
Input
Zo = 50 Ohm
R4
125
R1
84
LVPECL
3.3V
3.3V
Zo = 50 Ohm
F
IGURE
2D. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
3.3V
3.3V
CML Built-In Pullup
R1
100
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
Zo = 50 Ohm
Zo = 50 Ohm
R2
50
Zo = 50 Ohm
C1
R1
50
C2
PC L K /n PC LK
R5
100 - 200
Zo = 50 Ohm
R6
100 - 200
PCLK
nPCLK
VBB
3.3V LVPECL
3.3V
3.3V
LVDS
3.3V
Zo = 50 Ohm
3.3V
PCLK
nPCLK
VBB
R2
1K
C2
R1
1K
R5
100
C1
PC L K/n PC L K
Zo = 50 Ohm
85301AK
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
10
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50
transmission lines. Matched imped-
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
ance techniques should be used to maximize operating
frequency and minimize signal distortion.
Figures 3A and
3B
show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
I
NPUTS
:
PCLK/nPCLK I
NPUT
:
For applications not requiring the use of a differential input,
both the PCLK and nPCLK pins can be left floating. Though
not required, but for additional protection, a 1k
resistor can
be tied from PCLK to ground.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
P
INS
85301AK
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REV. A JANUARY 16, 2006
11
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 4A
and
Figure 4B
show examples of termination for
2.5V LVPECL driver. These terminations are equivalent to ter-
minating 50
to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is very
close to ground level. The R3 in Figure 4B can be eliminated
and the termination is shown in
Figure 4C.
F
IGURE
4C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
F
IGURE
4B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
F
IGURE
4A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
Zo = 50 Ohm
R1
250
+
-
2.5V
2,5V LVPECL
Driv er
R4
62.5
R3
250
Zo = 50 Ohm
2.5V
VCC=2.5V
R1
50
R3
18
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driv er
VCC=2.5V
2.5V
R2
50
2,5V LVPECL
Driv er
VCC=2.5V
R1
50
R2
50
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
+
-
85301AK
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REV. A JANUARY 16, 2006
12
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
A
PPLICATION
S
CHEMATIC
E
XAMPLE
Figure 5
shows an example of ICS85401 application sche-
matic. This device can accept different types of input signal.
In this example, the input is driven by a LVDS driver. The
Zo = 50
3.3V
+
-
C1
0.1u
R3
100
3.3V
3.3V
U1
ICS85401
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK0
nCLK0
CLK1
nCLK1
nc
C
L
K_
SE
L
nc
VD
D
GND
nQ
Q
GND
VD
D
GN
D
GN
D
nc
R2
100
LVDS
LVDS
3.3V
Zo = 50
C2
0.1u
Zo = 50
Zo = 50
R1
100
Zo = 50
R4
1K
Zo = 50
F
IGURE
5. ICS85401 A
PPLICATION
S
CHEMATIC
E
XAMPLE
decoupling capacitor should be located as close as possible
to the power pin.
85301AK
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REV. A JANUARY 16, 2006
13
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER


JA
at 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5C/W
T
ABLE
6A. T
HERMAL
R
ESISTANCE


JA
FOR
16-
PIN
VFQFN, F
ORCED
C
ONVECTION
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85301.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85301 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 26mA = 90.09mW
Power (outputs)
MAX
= 27.83mW/Loaded Output pair
Total Power
_MAX
(3.465, with all outputs switching) = 90.09mW + 27.83mW = 117.92mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 0 linear feet per minute and a multi-layer board, the appropriate value is 51.5C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.118W * 51.5C/W = 91.1C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
T
ABLE
6B. T
HERMAL
R
ESISTANCE


JA
FOR
FOR
16 L
EAD
TSSOP


JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
137.1C/W
118.2C/W
106.8C/W
Multi-Layer PCB, JEDEC Standard Test Boards
89.0C/W
81.8C/W
78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85301AK
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REV. A JANUARY 16, 2006
14
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 6.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
1.005V
(V
CC_MAX
- V
OH_MAX
) = 1.005
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.78V
(V
CC_MAX
- V
OL_MAX
) = 1.78V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 1.005V)/50
] * 1.005V = 20mW
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.78V)/50
] * 1.78V = 7.83mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 27.83mW
F
IGURE
6. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
VOUT
Q1
VCC - 2V
RL
50
VCC
85301AK
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REV. A JANUARY 16, 2006
15
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS85301 is: 137
T
ABLE
7A.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
16 L
EAD
VFQFN


JA
at 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5C/W
T
ABLE
7B.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
16 L
EAD
TSSOP


JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
137.1C/W
118.2C/W
106.8C/W
Multi-Layer PCB, JEDEC Standard Test Boards
89.0C/W
81.8C/W
78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85301AK
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
16
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
P
ACKAGE
O
UTLINE
- K S
UFFIX
FOR
16 L
EAD
VFQFN
T
ABLE
8A. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-220
N
O
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T
A
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85301AK
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
17
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
16 L
EAD
TSSOP
T
ABLE
8B. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
M
Y
S
s
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85301AK
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
18
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
T
ABLE
9. O
RDERING
I
NFORMATION
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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85301AK
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
19
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
T
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