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Datasheet: 011AL (Integrated Circuit Systems)

FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V LVPECL CLOCK GENERATOR

 

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Integrated Circuit Systems

Document Outline

843011AG
www.icst.com/products/hiperclocks.html
REV. B DECEMBER 10, 2004
1
Integrated
Circuit
Systems, Inc.
ICS843011
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS843011 is a Fibre Channel Clock Generator
and a member of the HiPerClocks
TM
family of high
performance devices from ICS. The ICS843011
uses a 26.5625MHz crystal to synthesize
106.25MHz or a 25MHz crystal to synthesize
100MHz. The ICS843011 has excellent <1ps phase jitter
performance, over the 637KHz 10MHz integration range. The
ICS843011 is packaged in a small 8-pin TSSOP, making it ideal
for use in systems with limited board space.
F
EATURES
1 differential 3.3V LVPECL output
Crystal oscillator interface designed for 26.5625MHz
18pF parallel resonant crystal
Output frequency: 106.25MHz or 100MHz
VCO range: 560MHz - 680MHz
RMS phase jitter @ 100MHz, using a 25MHz crystal
(637KHz - 10MHz): 0.80ps (typical)
RMS phase noise at 106.25MHz
Phase noise:
Offset
Noise Power
100Hz ............... -92.8 dBc/Hz
1KHz .............. -119.6 dBc/Hz
10KHz .............. -129.5 dBc/Hz
100KHz .............. -130.5 dBc/Hz
3.3V operating supply
Lead-Free package fully RoHS compliant
-40C to 85C ambient operating temperature
HiPerClockSTM
ICS
F
REQUENCY
T
ABLE
)
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1
ICS843011
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
Top View
V
CCA
V
EE
XTAL_OUT
XTAL_IN
1
2
3
4
V
CC
Q0
nQ0
nc
8
7
6
5
OSC
Phase
Detector
VCO
637.5MHz w/
26.5625MHz Ref.
M = 24 (fixed)
6
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
nQ0
Q0
XTAL_IN
XTAL_OUT
843011AG
www.icst.com/products/hiperclocks.html
REV. B DECEMBER 10, 2004
2
Integrated
Circuit
Systems, Inc.
ICS843011
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
1. P
IN
D
ESCRIPTIONS
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843011AG
www.icst.com/products/hiperclocks.html
REV. B DECEMBER 10, 2004
3
Integrated
Circuit
Systems, Inc.
ICS843011
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= -40C
TO
85C
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ABLE
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HARACTERISTICS
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A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
101.7C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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843011AG
www.icst.com/products/hiperclocks.html
REV. B DECEMBER 10, 2004
4
Integrated
Circuit
Systems, Inc.
ICS843011
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
T
YPICAL
P
HASE
N
OISE
AT
100MH
Z
100MHz
RMS Phase Noise Jitter
637K to 10MHz = 0.80ps (typical)
T
YPICAL
P
HASE
N
OISE
AT
106.25MH
Z
106.25MHz
RMS Phase Noise Jitter
637K to 10MHz = 0.80ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
Phase Noise Result by adding
a Filter to raw data
Raw Phase Noise Data
Filter
O
FFSET
F
REQUENCY
(H
Z
)
dBc
Hz
N
OISE
P
O
WER
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
Phase Noise Result by adding
Fibre Channel Filter to raw data
Raw Phase Noise Data
Fibre Channel Filter
dBc
Hz
N
OISE
P
O
WER
843011AG
www.icst.com/products/hiperclocks.html
REV. B DECEMBER 10, 2004
5
Integrated
Circuit
Systems, Inc.
ICS843011
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V 0.165V
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
Q0
nQ0
V
EE
V
CC
RMS P
HASE
J
ITTER
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
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