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Datasheet: IBM0418A4ACLAB-55 (IBM)

 

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crlh3320.06
12/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 27
IBM0418A4ACLAB
IBM0418A8ACLAB
IBM0436A8ACLAB
IBM0436A4ACLAB
Preliminary
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Features
8Mb: 256K x 36 or 512K x 18 organizations
4Mb: 128K x 36 or 256K x 18 organizations
0.25 Micron CMOS technology
Synchronous Register-Latch Mode of Operation
with Self-Timed Late Write
Single Differential HSTL Clock
+3.3V Power Supply, Ground, 2.0V max V
DDQ
,
and 0.85V V
REF
HSTL Input and Output levels
Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins
Latched Outputs
Common I/O
Asynchronous Output Enable
Synchronous Power Down Input
Boundary Scan using limited set of JTAG
1149.1 functions
Byte Write Capability & Global Write Enable
7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
Description
The 4 and 8Mb SRAM
S
--IBM0436A4ACLAB,
IBM0436A8ACLAB, IBM0418A4ACLAB, and
IBM0418A8ACLAB--are Synchronous Register-
Latch Mode, high-performance CMOS Static Ran-
dom Access Memories that are versatile, have wide
I/O, and can achieve 3.8 ns cycle times. Differential
K clocks are used to initiate the read/write operation
and all internal operations are self-timed. At the ris-
ing edge of the K clock, all Addresses, Write-
Enables, Sync Select, and Data Ins are registered
internally. Data Outs are updated from output regis-
ters off the falling edge of the K clock. An internal
Write buffer allows write data to follow one cycle
after addresses and controls. The chip is operated
with a single +3.3V power supply and is compatible
with HSTL I/O interface.
.
IBM0418A4ACLAB IBM0418A8ACLAB
IBM0436A8ACLAB IBM0436A4ACLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 2 of 27
crlh3320.06
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x36 BGA Pinout
(Top View)
1
2
3
4
5
6
7
A
V
DDQ
SA
SA
NC
SA
SA
V
DDQ
B
NC
NC
SA
NC
SA
NC, SA(8Mb)
NC
C
NC
SA
SA
V
DD
SA
SA
NC
D
DQ19
DQ18
V
SS
ZQ
V
SS
DQ9
DQ10
E
DQ22
DQ20
V
SS
SS
V
SS
DQ11
DQb13
F
V
DDQ
DQ21
V
SS
G
V
SS
DQ12
V
DDQ
G
DQ24
DQ23
SBWc
NC
SBWb
DQ14
DQb15
H
DQ25
DQ26
V
SS
NC
V
SS
DQ17
DQb16
J
V
DDQ
V
DD
V
REF
V
DD
V
REF
V
DD
V
DDQ
K
DQ34
DQ35
V
SS
K
V
SS
DQ8
DQ7
L
DQ33
DQ32
SBWd
K
SBWa
DQ5
DQ6
M
V
DDQ
DQ30
V
SS
SW
V
SS
DQ3
V
DDQ
N
DQ31
DQ29
V
SS
SA
V
SS
DQ2
DQ4
P
DQ28
DQ27
V
SS
SA
V
SS
DQ0
DQ1
R
NC
SA
M1*
V
DD
M2*
SA
NC
T
NC
NC
SA
SA
SA
NC
ZZ
U
V
DDQ
TMS
TDI
TCK
TDO
NC
V
DDQ
Note: * M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to V
DD
and V
SS
respectively.
x18 BGA Pinout
(Top View)
1
2
3
4
5
6
7
A
V
DDQ
SA
SA
NC
SA
SA
V
DDQ
B
NC
NC
SA
NC
SA
NC, SA(8Mb)
NC
C
NC
SA
SA
V
DD
SA
SA
NC
D
DQ14
NC
V
SS
ZQ
V
SS
DQ0
NC
E
NC
DQ15
V
SS
SS
V
SS
NC
DQ1
F
V
DDQ
NC
V
SS
G
V
SS
DQ2
V
DDQ
G
NC
DQ16
SBWb
NC
NC
NC
DQ3
H
DQ17
NC
V
SS
NC
V
SS
DQ4
NC
J
V
DDQ
V
DD
V
REF
V
DD
V
REF
V
DD
V
DDQ
K
NC
DQ13
V
SS
K
V
SS
NC
DQ8
L
DQ12
NC
NC
K
SBWa
DQ7
NC
M
V
DDQ
DQ10
V
SS
SW
V
SS
NC
V
DDQ
N
DQ11
NC
V
SS
SA
V
SS
DQ6
NC
P
NC
DQ9
V
SS
SA
V
SS
NC
DQ5
R
NC
SA
M1
V
DD
M2
SA
NC
T
NC
SA
SA
NC
SA
SA
ZZ
U
V
DDQ
TMS
TDI
TCK
TDO
NC
V
DDQ
Note: * M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to V
DD
and V
SS
respectively.
IBM0418A4ACLAB IBM0418A8ACLAB
IBM0436A8ACLAB IBM0436A4ACLAB
Preliminary
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
crlh3320.06
12/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 27
Pin Description
SA0-SA18
Address Input
SA0-SA18 for 512K x 18
SA0-SA17 for 256K x 36
SA0-SA17 for 256K x 18
SA0-SA16 for 128K x 36
G
Asynchronous Output Enable
DQ0-DQ35
Data I/O
DQ0-DQ17 for 512K x 18
DQ0-DQ35 for 256K x 36
SS
Synchronous Select
K, K
Differential Input Register Clocks
M1, M2
Clock Mode Inputs- Selects Single or Dual Clock
Operation.
SW
Write Enable, Global
V
REF
(2)
HSTL Input Reference Voltage
SBWa
Write Enable, Byte a (DQ0-DQ8)
V
DD
Power Supply (+3.3V)
SBWb
Write Enable, Byte b (DQ9-DQ17)
V
SS
Ground
SBWc
Write Enable, Byte c (DQ18-DQ26)
V
DDQ
Output Power Supply
SBWd
Write Enable, Byte d (DQ27-DQ35)
ZZ
Synchronous Sleep Mode
TMS, TDI, TCK
IEEE 1149.1 Test Inputs (LVTTL levels)
ZQ
Output Driver Impedance Control
TDO
IEEE 1149.1 Test Output (LVTTL level)
NC
No Connect
IBM0418A4ACLAB IBM0418A8ACLAB
IBM0436A8ACLAB IBM0436A4ACLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 4 of 27
crlh3320.06
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Ordering Information
Part Number
Organization
Speed
Leads
IBM0436A8ACLAB - 37
256K x 36
3.7ns Access / 3.8ns Cycle
7 x 17 BGA
IBM0436A8ACLAB - 43
256K x 36
4.2ns Access / 4.2ns Cycle
7 x 17 BGA
IBM0436A8ACLAB - 45
256K x 36
4.5ns Access / 4.5ns Cycle
7 x 17 BGA
IBM0436A8ACLAB - 50
256K x 36
5.0ns Access / 5.0ns Cycle
7 x 17 BGA
IBM0436A8ACLAB - 55
256K x 36
5.5ns Access /5.5ns Cycle
7 x 17 BGA
IBM0436A4ACLAB - 37
128K x 36
3.7ns Access / 3.8ns Cycle
7 x 17 BGA
IBM0436A4ACLAB - 43
128K x 36
4.2ns Access / 4.2ns Cycle
7 x 17 BGA
IBM0436A4ACLAB - 45
128K x 36
4.5ns Access / 4.5ns Cycle
7 x 17 BGA
IBM0436A4ACLAB - 50
128K x 36
5.0ns Access / 5.0ns Cycle
7 x 17 BGA
IBM0436A4ACLAB - 55
128K x 36
5.5ns Access /5.5ns Cycle
7 x 17 BGA
IBM0418A4ACLAB - 37
256K x 18
3.7ns Access / 3.8ns Cycle
7 x 17 BGA
IBM0418A4ACLAB - 43
256K x 18
4.2ns Access / 4.2ns Cycle
7 x 17 BGA
IBM0418A4ACLAB - 50
256K x 18
5.0ns Access / 5.0ns Cycle
7 x 17 BGA
IBM0418A4ACLAB - 55
256K x 18
5.5ns Access /5.5ns Cycle
7 x 17 BGA
IBM0418A8ACLAB - 37
512K x 18
3.7ns Access / 3.8ns Cycle
7 x 17 BGA
IBM0418A8ACLAB - 43
512K x 18
4.2ns Access / 4.2ns Cycle
7 x 17 BGA
IBM0418A8ACLAB -45
512K x 18
4.5ns Access / 4.5ns Cycle
7 x 17 BGA
IBM0418A8ACLAB -50
512K x 18
5.0ns Access / 5.0ns Cycle
7 x 17 BGA
IBM0418A8ACLAB -55
512K x 18
5.5ns Access /5.5ns Cycle
7 x 17 BGA
IBM0418A4ACLAB IBM0418A8ACLAB
IBM0436A8ACLAB IBM0436A4ACLAB
Preliminary
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
crlh3320.06
12/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 27
Block Diagram
SBW
Row Decode
Col Decode
Read/Wr Amp
DOC_Array0
SA0-SA18
K
ZZ
G
SW
SS
DQ0-DQ35
REG
REG
SBW
2:1 MUX
DOC_MUX0
WRITE1
ADD REG
WRITE0
ADD REG
READ
ADD REG
READ
WRITE
MATCH
MATCH1
LATCH
LATCH0
WR_BUF1
WR_BUF0
2:1 MUX
DOC_MUX1
2:1 MUX
DOC_MUX2
SBW0
SW0
SW1
REG
REG
DOC_
DOUT0
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