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Datasheet: IBM0418A41NLAB-4 (IBM)

 

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IBM0436A41NLAB IBM0418A41NLAB
IBM0418A81NLAB IBM0436A81NLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
crrL3325.06.fm
June 13, 2002
Page 1 of 25
Features
8Mb: 256K x 36 or 512K x 18 organizations
4Mb: 128K x 36 or 256K x 18 organizations
0.25 Micron CMOS technology
Synchronous pipeline mode of operation with
self-timed late write
Differential PECL clocks or 2.5V LVTTL swing
with one clock tied to V
DDQ
/2
+3.3V power supply, ground, 2.5V V
DDQ
2.5V LVTTL input and output levels
Registered addresses, write enables, synchro-
nous select, and data ins
Registered outputs
30
drivers
Common I/O
Asynchronous output enable
Synchronous power down input
Boundary scan using limited set of JTAG 1149.1
functions
Byte write capability and global write enable
7 x 17 bump ball grid array package with SRAM
JEDEC standard pinout and boundary SCAN
order
Description
The 4Mb and 8Mb SRAMs--IBM0436A41NLAB,
IBM0418A41NLAB, IBM0418A81NLAB, and
IBM0436A81NLAB--are synchronous pipeline
mode, high-performance CMOS static random-
access memories that are versatile, have wide I/O,
and can achieve 3.0ns cycle times. Differential K
clocks are used to initiate the read/write operation
and all internal operations are self-timed. At the ris-
ing edge of the K clock, all addresses, write-
enables, synchronous select, and data ins are regis-
tered internally. Data outs are updated from output
registers on the next rising edge of the K clock. An
internal write buffer allows write data to follow one
cycle after addresses and controls. The device is
operated with a single +3.3V power supply and is
compatible with a 2.5V LVTTL I/O interface.
.
IBM0436A41NLAB IBM0418A41NLAB
IBM0418A81NLAB IBM0436A81NLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Page 2 of 25
crrL3325.06.fm
June 13, 2002
x36 BGA Pinout
(Top View)
1
2
3
4
5
6
7
A
V
DDQ
SA
SA
NC
SA
SA
V
DDQ
B
NC
NC
SA
NC
SA
NC, SA (8Mb)
NC
C
NC
SA
SA
V
DD
SA
SA
NC
D
DQ19
DQ18
V
SS
NC
V
SS
DQ9
DQ10
E
DQ22
DQ20
V
SS
SS
V
SS
DQ11
DQb13
F
V
DDQ
DQ21
V
SS
G
V
SS
DQ12
V
DDQ
G
DQ24
DQ23
SBWc
NC
SBWb
DQ14
DQb15
H
DQ25
DQ26
V
SS
NC
V
SS
DQ17
DQb16
J
V
DDQ
V
DD
NC
V
DD
NC
V
DD
V
DDQ
K
DQ34
DQ35
V
SS
K
V
SS
DQ8
DQ7
L
DQ33
DQ32
SBWd
K
SBWa
DQ5
DQ6
M
V
DDQ
DQ30
V
SS
SW
V
SS
DQ3
V
DDQ
N
DQ31
DQ29
V
SS
SA
V
SS
DQ2
DQ4
P
DQ28
DQ27
V
SS
SA
V
SS
DQ0
DQ1
R
NC
SA
M1
1
V
DD
M2
1
SA
NC
T
NC
NC
SA
SA
SA
NC
ZZ
U
V
DDQ
TMS
TDI
TCK
TDO
NC
V
DDQ
1. M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to V
SS
and V
DD
,
respectively.
x18 BGA Pinout
(Top View)
1
2
3
4
5
6
7
A
V
DDQ
SA
SA
NC
SA
SA
V
DDQ
B
NC
NC
SA
NC
SA
NC, SA (8Mb)
NC
C
NC
SA
SA
V
DD
SA
SA
NC
D
DQ14
NC
V
SS
NC
V
SS
DQ0
NC
E
NC
DQ15
V
SS
SS
V
SS
NC
DQ1
F
V
DDQ
NC
V
SS
G
V
SS
DQ2
V
DDQ
G
NC
DQ16
SBWb
NC
NC
NC
DQ3
H
DQ17
NC
V
SS
NC
V
SS
DQ4
NC
J
V
DDQ
V
DD
NC
V
DD
NC
V
DD
V
DDQ
K
NC
DQ13
V
SS
K
V
SS
NC
DQ8
L
DQ12
NC
NC
K
SBWa
DQ7
NC
M
V
DDQ
DQ10
V
SS
SW
V
SS
NC
V
DDQ
N
DQ11
NC
V
SS
SA
V
SS
DQ6
NC
P
NC
DQ9
V
SS
SA
V
SS
NC
DQ5
R
NC
SA
M1
1
V
DD
M2
1
SA
NC
T
NC
SA
SA
NC
SA
SA
ZZ
U
V
DDQ
TMS
TDI
TCK
TDO
NC
V
DDQ
1. M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to V
SS
and V
DD
, respectively.
IBM0436A41NLAB IBM0418A41NLAB
IBM0418A81NLAB IBM0436A81NLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
crrL3325.06.fm
June 13, 2002
Page 3 of 25
Pin Description
SA0-SA18
Address Input
SA0-SA18 for 512K x 18
SA0-SA17 for 256K x 36
SA0-SA17 for 256K x 18
SA0-SA16 for 128K x 36
G
Asynchronous Output Enable
DQ0-DQ35
Data I/O
DQ0-DQ17 for 512K x 18
DQ0-DQ35 for 256K x 36
SS
Synchronous Select
K, K
Differential Input Register Clocks
M1, M2
Clock Mode Inputs - Selects Single or Dual
Clock Operation.
SW
Write Enable, Global
V
DD
Power Supply (+3.3V)
SBWa
Write Enable, Byte a (DQ0-DQ8)
V
SS
Ground
SBWb
Write Enable, Byte b (DQ9-DQ17)
V
DDQ
Output Power Supply
SBWc
Write Enable, Byte c (DQ18-DQ26)
ZZ
Synchronous Sleep Mode
SBWd
Write Enable, Byte d (DQ27-DQ35)
NC
No Connect
TMS, TDI, TCK
IEEE
1149.1 Test Inputs (LVTTL levels)
TDO
IEEE 1149.1 Test Output (LVTTL level)
IBM0436A41NLAB IBM0418A41NLAB
IBM0418A81NLAB IBM0436A81NLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Page 4 of 25
crrL3325.06.fm
June 13, 2002
Ordering Information
Part Number
Organization
Speed
Leads
IBM0418A41NLAB - 3
256K x 18
1.8ns Access / 3.0ns Cycle
7 x 17 BGA
IBM0418A41NLAB - 3F
256K x 18
2.0ns Access / 3.3ns Cycle
7 x 17 BGA
IBM0418A41NLAB - 3N
256K x 18
2.0ns Access / 3.7ns Cycle
7 x 17 BGA
IBM0418A41NLAB - 4
256K x 18
2.25ns Access / 4.0ns Cycle
7 x 17 BGA
IBM0418A41NLAB - 5
256K x 18
2.5ns Access / 5.0ns Cycle
7 x 17 BGA
IBM0436A41NLAB - 3
128K x 36
1.8ns Access / 3.0ns Cycle
7 x 17 BGA
IBM0436A41NLAB - 3F
128K x 36
2.0ns Access / 3.3ns Cycle
7 x 17 BGA
IBM0436A41NLAB - 3N
128K x 36
2.0ns Access / 3.7ns Cycle
7 x 17 BGA
IBM0436A41NLAB - 4
128K x 36
2.25ns Access / 4.0ns Cycle
7 x 17 BGA
IBM0436A41NLAB - 5
128K x 36
2.5ns Access / 5.0ns Cycle
7 x 17 BGA
IBM0418A81NLAB - 3
512K x 18
1.8ns Access / 3.0ns Cycle
7 x 17 BGA
IBM0418A81NLAB - 3F
512K x 18
2.0ns Access / 3.3ns Cycle
7 x 17 BGA
IBM0418A81NLAB - 3N
512K x 18
2.0ns Access / 3.7ns Cycle
7 x 17 BGA
IBM0418A81NLAB - 4
512K x 18
2.25ns Access / 4.0ns Cycle
7 x 17 BGA
IBM0418A81NLAB - 5
512K x 18
2.5ns Access / 5.0ns Cycle
7 x 17 BGA
IBM0436A81NLAB - 3
256K x 36
1.8ns Access / 3.0ns Cycle
7 x 17 BGA
IBM0436A81NLAB - 3F
256K x 36
2.0ns Access / 3.3ns Cycle
7 x 17 BGA
IBM0436A81NLAB - 3N
256K x 36
2.0ns Access / 3.7ns Cycle
7 x 17 BGA
IBM0436A81NLAB - 4
256K x 36
2.25ns Access / 4.0ns Cycle
7 x 17 BGA
IBM0436A81NLAB - 5
256K x 36
2.5ns Access / 5.0ns Cycle
7 x 17 BGA
IBM0436A41NLAB IBM0418A41NLAB
IBM0418A81NLAB IBM0436A81NLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
crrL3325.06.fm
June 13, 2002
Page 5 of 25
Block Diagram
SBW
Row De
co
de
Col Decode
Read/Wr Amp
DOC_Array0
SA0-SA18
K
ZZ
G
SW
SS
DQ0-DQ35
REG
REG
SB
W
2:
1 M
U
X
DOC_MUX0
WRI
T
E
1
ADD REG
WRI
T
E
0
ADD REG
READ
ADD REG
READ
WR
ITE
MA
TCH
MATCH1
LATCH
LATCH0
WR_
B
U
F
1
WR_
B
U
F
0
2:1 MUX
DOC_MUX1
2:1 MUX
DOC_MUX2
SB
W
0
SW0
SW1
REG
REG
DOC_
DOUT0
REG
REG
SS1
SS0
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