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Datasheet: IBM0418A41DLAB-3F (IBM)

 

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IBM0436A41DLAB IBM0418A41DLAB
IBM0418A81DLAB IBM0436A81DLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
crrh3319.10.fm.00
June 12, 2002
Page 1 of 25
Features
8Mb: 256K x 36 or 512K x 18 organizations
4Mb: 128K x 36 or 256K x 18 organizations
0.25 Micron CMOS technology
Synchronous pipeline mode of operation with
self-timed late write
Single differential high-speed transceiver logic
(HSTL) Clock
+3.3V power supply, ground, 2.1V V
DDQ
, and
1.0V V
REF
HSTL input and output levels
Registered addresses, write enables, synchro-
nous select, and data-ins
Registered outputs
Common I/O
Asynchronous output enable
Synchronous power down input
Boundary scan using limited set of JTAG 1149.1
functions
Byte write capability and global write enable
7 x 17 bump ball grid array package with SRAM
JEDEC standard pinout and boundary SCAN
order
Description
The 4Mb and 8Mb SRAMs--IBM0436A41DLAB,
IBM0418A41DLAB, IBM0418A81DLAB, and
IBM0436A81DLAB--are synchronous pipeline
mode, high-performance CMOS static random
access memories that are versatile, have wide I/O,
and can achieve 3ns cycle times. Dual differential K
clocks are used to initiate the read/write operation
and all internal operations are self-timed. At the ris-
ing edge of the K clock, all addresses, write-
enables, synchronous select, and data ins are regis-
tered internally. Data outs are updated from output
registers on the next rising edge of the K clock. An
internal write buffer allows write data to follow one
cycle after addresses and controls. The SRAM is
operated with a single +3.3V power supply and is
compatible with HSTL I/O interfaces.
.
IBM0436A41DLAB IBM0418A41DLAB
IBM0418A81DLAB IBM0436A81DLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Page 2 of 25
crrh3319.10.fm.00
June 12, 2002
x36 BGA Pinout
(Top View)
1
2
3
4
5
6
7
A
V
DDQ
SA
SA
NC
SA
SA
V
DDQ
B
NC
NC
SA
NC
SA
NC,SA(8Mb)
NC
C
NC
SA
SA
V
DD
SA
SA
NC
D
DQ19
DQ18
V
SS
ZQ
V
SS
DQ9
DQb10
E
DQ22
DQ20
V
SS
SS
V
SS
DQ11
DQb13
F
V
DDQ
DQ21
V
SS
G
V
SS
DQ12
V
DDQ
G
DQ24
DQ23
SBWc
NC
SBWb
DQ14
DQb15
H
DQ25
DQ26
V
SS
NC
V
SS
DQ17
DQb16
J
V
DDQ
V
DD
V
REF
V
DD
V
REF
V
DD
V
DDQ
K
DQ34
DQ35
V
SS
K
V
SS
DQ8
DQ7
L
DQ33
DQ32
SBWd
K
SBWa
DQ5
DQ6
M
V
DDQ
DQ30
V
SS
SW
V
SS
DQ3
V
DDQ
N
DQ31
DQ29
V
SS
SA0
V
SS
DQ2
DQ4
P
DQ28
DQ27
V
SS
SA1
V
SS
DQ0
DQ1
R
NC
SA
M1
1
V
DD
M2
1
SA
NC
T
NC
NC
SA
SA
SA
NC
ZZ
U
V
DDQ
TMS
TDI
TCK
TDO
NC
V
DDQ
1. M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to V
SS
and V
DD
, respectively.
x18 BGA Pinout
(Top View)
1
2
3
4
5
6
7
A
V
DDQ
SA
SA
NC
SA
SA
V
DDQ
B
NC
NC
SA
NC
SA
NC,SA(8Mb)
NC
C
NC
SA
SA
V
DD
SA
SA
NC
D
DQ14
NC
V
SS
ZQ
V
SS
DQ0
NC
E
NC
DQ15
V
SS
SS
V
SS
NC
DQ1
F
V
DDQ
NC
V
SS
G
V
SS
DQ2
V
DDQ
G
NC
DQ16
SBWb
NC
NC
NC
DQ3
H
DQ17
NC
V
SS
NC
V
SS
DQ4
NC
J
V
DDQ
V
DD
V
REF
V
DD
V
REF
V
DD
V
DDQ
K
NC
DQ13
V
SS
K
V
SS
NC
DQ8
L
DQ12
NC
NC
K
SBWa
DQ7
NC
M
V
DDQ
DQ10
V
SS
SW
V
SS
NC
V
DDQ
N
DQ11
NC
V
SS
SA0
V
SS
DQ6
NC
P
NC
DQ9
V
SS
SA1
V
SS
NC
DQ5
R
NC
SA
M1
1
V
DD
M2
1
SA
NC
T
NC
SA
SA
NC
SA
SA
ZZ
U
V
DDQ
TMS
TDI
TCK
TDO
NC
V
DDQ
1. M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to V
SS
and V
DD
respectively.
IBM0436A41DLAB IBM0418A41DLAB
IBM0418A81DLAB IBM0436A81DLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
crrh3319.10.fm.00
June 12, 2002
Page 3 of 25
Pin Description
SA0-SA18
Address Input
SA0-SA18 for 512K x 18
SA0-SA17 for 256K x 36
SA0-SA17 for 256K x 18
SA0-SA16 for 128K x 36
G
Asynchronous Output Enable
DQ0-DQ35
Data I/O
DQ0-DQ17 for 512K x 18
DQ0-DQ35 for 256K x 36
SS
Synchronous Select
K, K
Differential Input Register Clocks
M1, M2
Clock Mode Inputs - Selects Single or Dual
Clock Operation.
SW
Write Enable, Global
V
REF
(2)
HSTL Input Reference Voltage
SBWa
Write Enable, Byte a (DQ0-DQ8)
V
DD
Power Supply (+3.3V)
SBWb
Write Enable, Byte b (DQ9-DQ17)
V
SS
Ground
SBWc
Write Enable, Byte c (DQ18-DQ26)
V
DDQ
Output Power Supply
SBWd
Write Enable, Byte d (DQ27-DQ35)
ZZ
Synchronous Sleep Mode
TMS,TDI,TCK
IEEE
1149.1 Test Inputs (LVTTL levels)
ZQ
Output Driver Impedance Control
TDO
IEEE 1149.1 Test Output (LVTTL level)
NC
No Connect
Ordering Information
(All possible types are listed; some may not be qualified.)
Part Number
Organization
Speed
Leads
IBM0418A41DLAB - 3
256K x 18
1.7ns Access / 3.0ns Cycle
7 x 17 BGA
IBM0418A41DLAB - 3F
256K x 18
1.8ns Access / 3.3ns Cycle
7 x 17 BGA
IBM0418A41DLAB - 4
256K x 18
2.0ns Access / 4.0ns Cycle
7 x 17 BGA
IBM0418A41DLAB - 5
256K x 18
2.25ns Access /5.0ns Cycle
7 x 17 BGA
IBM0436A41DLAB - 3
128K x 36
1.7ns Access / 3.0ns Cycle
7 x 17 BGA
IBM0436A41DLAB - 3F
128K x 36
2.0ns Access / 3.3ns Cycle
7 x 17 BGA
IBM0436A41DLAB - 4
128K x 36
2.0ns Access / 4.0ns Cycle
7 x 17 BGA
IBM0436A41DLAB - 5
128K x 36
2.25ns Access /5.0ns Cycle
7 x 17 BGA
IBM0418A81DLAB - 3
512K x 18
1.7ns Access / 3.0ns Cycle
7 x 17 BGA
IBM0418A81DLAB - 3F
512K x 18
1.8ns Access / 3.3ns Cycle
7 x 17 BGA
IBM0418A81DLAB - 4
512K x 18
2.0ns Access / 4.0ns Cycle
7 x 17 BGA
IBM0418A81DLAB - 5
512K x 18
2.25ns Access /5.0ns Cycle
7 x 17 BGA
IBM0436A81DLAB - 3
256K x 36
1.7ns Access / 3.0ns Cycle
7 x 17 BGA
IBM0436A81DLAB -3F
256K x 36
1.8ns Access / 3.3ns Cycle
7 x 17 BGA
IBM0436A81DLAB - 4
256K x 36
2.0ns Access / 4.0ns Cycle
7 x 17 BGA
IBM0436A81DLAB - 5
256K x 36
2.25ns Access /5.0ns Cycle
7 x 17 BGA
IBM0436A41DLAB IBM0418A41DLAB
IBM0418A81DLAB IBM0436A81DLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Page 4 of 25
crrh3319.10.fm.00
June 12, 2002
Block Diagram
SBW
Row De
co
de
Col Decode
Read/Wr Amp
DOC_Array0
SA0-SA18
K
ZZ
G
SW
SS
DQ0-DQ35
REG
REG
SB
W
2:
1 M
U
X
DOC_MUX0
WRI
T
E
1
ADD
RE
G
WRI
T
E
0
ADD REG
READ
ADD REG
READ
WR
ITE
MA
TCH
MATCH1
LATCH
LATCH0
WR_
B
U
F
1
WR_
B
U
F
0
2:1 MUX
DOC_MUX1
2:1 MUX
DOC_MUX2
SB
W
0
SW0
SW1
REG
REG
DOC_
DOUT0
REG
REG
SS1
SS0
IBM0436A41DLAB IBM0418A41DLAB
IBM0418A81DLAB IBM0436A81DLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
crrh3319.10.fm.00
June 12, 2002
Page 5 of 25
SRAM Features
Late Write
The late write function allows write data to be registered one cycle after addresses and controls. This feature
eliminates one bus-turnaround cycle, necessary when going from a read to a write operation. Late write is
accomplished by buffering write addresses and data so that the write operation occurs during the next write
cycle. When a read cycle occurs after a write cycle, the address and write data information are stored tempo-
rarily in holding registers. During the first write cycle preceded by a read cycle, the SRAM array will be
updated with address and data from the holding registers. Read cycle addresses are monitored to determine
if read data is to be supplied from the SRAM array or the write buffer. The bypassing of the SRAM array
occurs on a byte-by-byte basis. When only one byte is written during a write cycle, read data from the last
written address will have new byte data from the write buffer and remaining bytes from the SRAM array.
Mode Control
Mode control pins M1 and M2 are used to select four different JEDEC-standard read protocols. This SRAM
supports a single clock pipeline (M1 = V
SS
, M2 = V
DD
). This datasheet only describes single clock pipeline
functionality. Mode control inputs must be set at power up and must not change during SRAM operation. This
SRAM is tested only in the pipeline mode.
Sleep Mode
Sleep mode is enabled by switching synchronous signal ZZ high. When the SRAM is in sleep mode, the out-
puts will go to a High-Z state and the SRAM will draw standby current. SRAM data will be preserved and a
recovery time (t
ZZR
) is required before the SRAM resumes normal operation.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V
SS
to allow the SRAM to
adjust its output driver impedance. The value of RQ must be five times the value of the intended line imped-
ance driven by the SRAM. The allowable range of RQ to guarantee impedance matching is between 175
and 350
, with the tolerance described in Programmable Impedance Output Driver DC Electrical Character-
istics on page 9. The RQ resistor should be placed less than two inches away from the ZQ ball on the SRAM
module. The total external capacitance (including wiring) seen by the ZQ ball should be minimized (less than
7.5 pF).
Programmable Impedance and Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by
drifts in supply voltage and temperature. One evaluation occurs every 64 clock cycles and each evaluation
may move the output driver impedance level only one step at a time towards the optimum level. The output
driver has 32 discrete binary weighted steps. The impedance update of the output driver occurs when the
SRAM is in High-Z. Write and deselect operations will synchronously switch the SRAM into and out of High-Z,
thereby triggering an update. The user may choose to invoke asynchronous G updates by providing a G
setup and hold times around the K clock to guarantee the proper update. There are no power-up require-
ments for the SRAM; however, to guarantee optimum output driver impedance after power up, the SRAM
needs 4096 clock cycles followed by a Low-Z to High-Z transition.
Power-Up and Power-Down Sequencing
The power supplies need to be powered up in the following order: V
DD
, V
DDQ
, V
REF
, and inputs. The power-
down sequencing must be in the reverse order. V
DDQ
can be allowed to exceed V
DD
by no more than 0.6V.
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