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Datasheet: IBM04188ETLAC-37 (IBM)

 

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IBM04188ETLAC
IBM04368ETLAC
8Mb (256K x 36 & 512K x 18) SRAM
ETLAC_ds.fm.00
June 07, 2002
Page 1 of 24
Features
256K x 36 or 512K x 18 organization
CMOS technology
Synchronous late-select mode of operation with
self-timed late write
Single differential high-speed transceiver logic
(HSTL) clock
3.3V power supply, 1.5V V
DDQ
HSTL input and output levels
Registered addresses, write enables, synchro-
nous select and data-ins.
Common I/O
Asynchronous output enable and sleep mode
inputs
Boundary scan using a limited set of JTAG
1149.1 functions
Byte write capability and global write enable
7 x 17 bump ball grid array package with SRAM
JEDEC standard pinout and boundary scan
order
Programmable impedance output drivers
Description
The 3.3V IBM04188ETLAC and IBM04368ETLAC
SRAMs are synchronous pipeline-mode, late select,
high-performance CMOS static random-access
memories that have wide I/O and achieve 3ns cycle
times. Single differential K clocks are used to initiate
the read/write operation, and all internal operations
are self-timed. At the rising edge of the K clock, all
addresses, write-enables, synchronous select, and
data-ins are registered internally. Data-outs are
updated from output registers on the next rising
edge of the K clock. An internal write buffer allows
write data to follow one cycle after addresses and
controls. Address SAS is a late-select address. It
performs a one-of-two decode on the data
addressed by addresses SA1SA18 in the previous
cycle. The SRAM is operated with a single 3.3V
power supply and is compatible with 1.5V HSTL I/O
interfaces.
.
IBM04188ETLAC
IBM04368ETLAC
8Mb (256K x 36 & 512K x 18) SRAM
Page 2 of 24
ETLAC_ds.fm.00
June 07, 2002
x36 BGA Bump Layout (Top View)
1
2
3
4
5
6
7
A
V
DDQ
SA14
SA11
NC
SA10
SA7
V
DDQ
B
NC
NC
SA13
NC
SA9
SA6
NC
C
NC
SA15
SA12
V
DD
SA8
SA5
NC
D
DQ21
DQ20
V
SS
ZQ
V
SS
DQ15
DQ14
E
DQ24
DQ22
V
SS
SS
V
SS
DQ13
DQ11
F
V
DDQ
DQ23
V
SS
G
V
SS
DQ12
V
DDQ
G
DQ19
DQ18
SBWc
NC
SBWb
DQ17
DQ16
H
DQ25
DQ26
V
SS
NC
V
SS
DQ9
DQ10
J
V
DDQ
V
DD
V
REF
V
DD
V
REF
V
DD
V
DDQ
K
DQ28
DQ27
V
SS
K
V
SS
DQ8
DQ7
L
DQ34
DQ35
SBWd
K
SBWa
DQ0
DQ1
M
V
DDQ
DQ30
V
SS
SW
V
SS
DQ5
V
DDQ
N
DQ29
DQ31
V
SS
SA1
V
SS
DQ4
DQ6
P
DQ32
DQ33
V
SS
SAS
V
SS
DQ2
DQ3
R
NC
SA16
M1
1
V
DD
M2
1
SA4
NC
T
NC
NC
SA17
SA2
SA3
NC
ZZ
U
V
DDQ
TMS
TDI
TCK
TDO
NC
V
DDQ
1. M1 and M2 are clock mode pins that must be connected to V
SS
and V
SS
respectively.
x18 BGA Bump Layout (Top View)
1
2
3
4
5
6
7
A
V
DDQ
SA14
SA11
NC
SA10
SA7
V
DDQ
B
NC
NC
SA13
NC
SA9
SA6
NC
C
NC
SA15
SA12
V
DD
SA8
SA5
NC
D
DQ10
NC
V
SS
ZQ
V
SS
DQ7
NC
E
NC
DQ11
V
SS
SS
V
SS
NC
DQ6
F
V
DDQ
NC
V
SS
G
V
SS
DQ5
V
DDQ
G
NC
DQ9
SBWc
NC
NC
NC
DQ8
H
DQ12
NC
V
SS
NC
V
SS
DQ4
NC
J
V
DDQ
V
DD
V
REF
V
DD
V
REF
V
DD
V
DDQ
K
NC
DQ13
V
SS
K
V
SS
NC
DQ3
L
DQ17
NC
NC
K
SBWa
DQ0
NC
M
V
DDQ
DQ14
V
SS
SW
V
SS
NC
V
DDQ
N
DQ15
NC
V
SS
SA1
V
SS
DQ2
NC
P
NC
DQ16
V
SS
SAS
V
SS
NC
DQ1
R
NC
SA16
M1
1
V
DD
M2
1
SA4
NC
T
NC
SA18
SA17
NC
SA3
SA2
ZZ
U
V
DDQ
TMS
TDI
TCK
TDO
NC
V
DDQ
1. M1 and M2 are clock mode pins that must be connected to V
SS
and V
SS
respectively.
IBM04188ETLAC
IBM04368ETLAC
8Mb (256K x 36 & 512K x 18) SRAM
ETLAC_ds.fm.00
June 07, 2002
Page 3 of 24
Pin Description
SA1SA18
Address Input
G
Asynchronous Output Enable
SAS
Late Select Address Input
SS
Synchronous Select
DQ0DQ35
Data I/O
M1, M2
Clock Mode Inputs-
M1 must be set to V
SS
M2 must be set to V
DD
K, K
Differential Input Register Clocks
V
REF
HSTL Input Reference Voltage
SW
Write Enable, Global
V
DD
Power Supply (+3.3V)
SBWa
Write Enable, Byte a (DQ0DQ8)
V
SS
Ground
SBWb
Write Enable, Byte b (DQ9DQ17)
V
DDQ
Output Power Supply
SBWc
Write Enable, Byte c (DQ18DQ26)
ZZ
Asynchronous Sleep Mode
SBWd
Write Enable, Byte d (DQ27DQ35)
ZQ
Output Driver Impedance Control
TMS, TDI, TCK
IEEE
1149.1 Test Inputs (LVTTL levels)
NC
No Connect
TDO
IEEE 1149.1 Test Output (LVTTL level)
Ordering Information
Part Number
Organization
Cycle Time (ns)
Package
IBM04188ETLAC-28
512K x 18
2.85
7 x 17 BGA
IBM04188ETLAC-30
512K x 18
3.0
7 x 17 BGA
IBM04188ETLAC-33
512K x 18
3.3
7 x 17 BGA
IBM04188ETLAC-37
512K x 18
3.7
7 x 17 BGA
IBM04368ETLAC-28
256K x 36
2.85
7 x 17 BGA
IBM04368ETLAC-30
256K x 36
3.0
7 x 17 BGA
IBM04368ETLAC-33
256K x 36
3.3
7 x 17 BGA
IBM04368ETLAC-37
256K x 36
3.7
7 x 17 BGA
IBM04188ETLAC
IBM04368ETLAC
8Mb (256K x 36 & 512K x 18) SRAM
Page 4 of 24
ETLAC_ds.fm.00
June 07, 2002
Block Diagram
128K x72
Buffer
Write
Column Decoder
Read/Write Amp
Ro
w Decoder
2:1 Mux
2:
1 M
u
x
Data Out
Register
DQ0-DQ35 or DQ0-DQ17
WR Add
Register
RD Add
Register
Mat
c
h
Latch
Latch
K
ZZ
SA1SA18, SAS
SW
SBW
SBW
Register
SBW
Register
SW
G
Register
Register
SS
SS
SS
SW
Register
Register
Array
2:1 Mux
36
SAS
36
36
IBM04188ETLAC
IBM04368ETLAC
8Mb (256K x 36 & 512K x 18) SRAM
ETLAC_ds.fm.00
June 07, 2002
Page 5 of 24
SRAM Features
Late Write
The late-write function allows write data to be registered one cycle after addresses and controls. This feature
eliminates one of two bus-turnaround cycles normally required when going from a read to a write operation.
Late write is accomplished by buffering write addresses and data. The SRAM array update occurs during the
third write cycle. Read-cycle addresses are monitored to determine if read data is to be supplied from the
SRAM array or the write buffer. The bypassing of the SRAM array occurs on a byte-by-byte basis. When one
byte is written during a write cycle, read data from the last written address has new byte data from the write
buffer and remaining bytes from the SRAM array.
Mode Control
Mode control pin M1 must be set to V
SS
and M2 to V
SS
.
Sleep Mode
Sleep mode is enabled by switching asynchronous signal ZZ high. When the SRAM is in sleep mode, the out-
puts go to a High-Z state and the SRAM draws standby current. SRAM data is preserved and a recovery time
(t
ZZR
) is required before the SRAM resumes normal operation.
Programmable Impedance and Power Up Requirements
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V
SS
to allow the SRAM to
adjust its output driver impedance. The value of RQ must be five times the value of the intended line imped-
ance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of
15% is between 175
and 350. Periodic readjustment of the output driver impedance is necessary because
the impedance is affected by drifts in supply voltage and temperature. One evaluation occurs every 64 clock
cycles, and each evaluation can move the output driver impedance level one step at a time towards the opti-
mum level. The output driver has 64 discrete binary weighted steps. Impedance updates for zeros occur
whenever the SRAM is driving ones for the same DQs; impedance updates for ones occur whenever the
SRAM is driving zeros. Updates of both zeros and ones occur when the SRAM is in High-Z. The SRAM
requires 4
s of power-up time after V
DD
reaches its operating range. Furthermore, to guarantee the output
driver impedance, the SRAM requires 2048 clock cycles and a Read `0' and Read `1' or a Read `1' and a
Read `0' across all outputs. The RC time constant of the loaded RQ trace must be less than 3ns.
Power-Up and Power-Down Sequence
The power supplies need to be powered up in the following sequence:
V
DD
, V
DDQ
, V
REF
, followed by inputs
The power-down sequence must be in the reverse order. V
DDQ
must not exceed V
DD
.
Late Select
Address SAS is the late select address. It is registered along with addresses SA1SA18. The pipelined data
clocked out in cycle n+1 is selected by addresses SA1SA18 and registered in cycle n, and SAS is registered
in cycle n+1.
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